Address translation for scalable virtualization of input/output devices

Patent metadata

Field	Value
Publication number	US-10509729-B2
Application number	US-201614994393-A
Country	US
Kind code	B2
Filing date	Jan 13, 2016
Priority date	Jan 13, 2016
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

Embodiments of an invention for address translation for scalable I/O device virtualization are disclosed. In one embodiment, an apparatus includes PASID table lookup circuitry. The PASID table lookup circuitry is to find a PASID-entry in a PASID table. The PASID-entry is to include a PASID processing mode (PPM) indicator and a first pointer to a first translation structure. The PPM indicator is to specify one of a plurality of translation types, the one of the plurality of translation types to use the first translation structure.

First claim

What is claimed is:

1. An apparatus comprising:
process address space identifier (PASID) table lookup circuitry to use a PASID from a memory access transaction to find a PASID-entry in a PASID table, wherein the PASID is assigned to a command portal through which a client is to submit a work request to an input/output device;
the PASID-entry to include a PASID processing mode (PPM) indicator, a first pointer to a first translation structure, and a second pointer to a second translation structure;
wherein the PPM indicator is to specify which of three translation modes is to be used in an address translation, the three translation modes to include a first mode in which only the first translation structure is to be used, a second mode in which only the second translation structure is to be used, and a third mode in which both the first and the second translation structures are to be used; and
context table lookup circuitry to find a context-entry in a context table, the context-entry to point to the PASID table and to include a translation-type field to specify whether to block the memory access transaction if it does not include the PASID instead of enabling single-root input/output virtualization if the memory access transaction does not include the PASID.

2. The apparatus of claim 1 , further comprising root table lookup circuitry to find a root-entry in a root table, the root-entry to point to the context table.

3. The apparatus of claim 1 , wherein the address translation is to be performed on an address from the memory access transaction.

4. The apparatus of claim 1 , wherein the address translation is from a virtual address to a host physical address.

5. The apparatus of claim 1 , wherein the address translation is from a guest physical address to a host physical address.

6. The apparatus of claim 1 , wherein the address translation is to include a host physical address filtering.

7. The apparatus of claim 1 , wherein the address translation is from a direct memory access address to a host physical address.

8. The apparatus of claim 1 , wherein the address translation is from a guest virtual address to a host physical address.

9. A method comprising:
assigning a process address space identifier (PASID) to a command portal through which a client is to submit a work request to an input/output device;
finding a context-entry in a context table, the context-entry to point to a PASID table;
determining, based on a translation-type field in the context-entry, whether to block a memory access transaction if it does not include the PASID instead of enabling single-root input/output virtualization if the memory access transaction does not include the PASID;
using the PASID to find a PASID-entry in a PASID-entry in the PASID table, the PASID-entry to include a PASID processing mode (PPM) indicator, a first pointer to a first translation structure, and a second pointer to a second translation structure, wherein the PPM indicator is to specify which of three translation modes is to be used in an address translation, the three translation modes to include a first mode in which only the first translation structure is to be used, a second mode in which only the second translation structure is to be used, and a third mode in which both the first and the second translation structures are to be used; and
performing the address translation in the specified mode.

10. The method of claim 9 , further comprising finding a root-entry in a root table, the root-entry to point to the context table.

11. The method of claim 9 , wherein the address translation is from a virtual address to a host physical address.

12. The method of claim 9 , wherein the address translation is a guest physical address to a host physical address translation.

13. The method of claim 9 , wherein the address translation is to include a host physical address filtering.

14. The method of claim 9 , wherein the address translation is from a direct memory access address to a host physical address.

15. The method of claim 9 , wherein the address translation is from a guest virtual address to a host physical address.

16. A system comprising:
a system memory;
an input/output device to initiate a transaction to the system memory; and
an input/output memory management unit, including:
process address space identifier (PASID) table lookup circuitry to find, using a PASID from the transaction, a PASID-entry in a PASID table, wherein the PASID is assigned to a command portal through which a client is to submit a work request to the input/output device, the PASID-entry to include a PASID processing mode (PPM) indicator, a first pointer to a first translation structure, and a second pointer to a second translation structure, wherein the PPM indicator is to specify which of three translation modes is to be used in an address translation, the three translation modes to include a first mode in which only the first translation structure is to be used, a second mode in which only the second translation structure is to be used, and a third mode in which both the first and the second translation structures are to be used; and
context table lookup circuitry to find a context-entry in a context table, the context-entry to point to the PASID table and to include a translation-type field to specify whether to block the transaction if it does not include the PASID instead of enabling single-root input/output virtualization if the memory access transaction does not include the PASID.

Assignees

• Intel Corp

Inventors

• Sankaran Rajesh M
• Campbell Randolph L
• Sethi Prashant
• Harriman David J

Classifications

• G06F2212/657

  Virtual address space management · CPC title

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title