Method and apparatus to control a link power state

Patent metadata

Field	Value
Publication number	US-10509455-B2
Application number	US-201815860300-A
Country	US
Kind code	B2
Filing date	Jan 2, 2018
Priority date	Dec 24, 2014
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A method is provided for controlling a link. This may include determining a condition of a first device coupled to the link, receiving, at the first device, a request for a specific link state from a second device coupled to the link, and determining a power state of the link based on the determined condition of the first device.

First claim

What is claimed is:

1. A non-transitory machine-readable medium comprising instructions that when executed cause a system on chip (SoC) coupled to a link to perform operations to:
identify a condition of a platform including I/O devices located externally from the SoC and further including at least one component of the SoC or another device coupled to the link, wherein the at least one component is located on the SoC, wherein to identify the condition includes at least one of to identify a first power state of the platform and to identify a second power state of the platform, wherein the second power state is greater than the first power state; and
in response to receipt, by the SoC, of a request for a specific link state, the request originating from one of the I/O devices of the platform:
determine a first power state of the link based only on identification of the first power state of the platform; and
determine a second power state of the link based only on identification of the second power state of the platform, wherein the second power state of the link is greater than the first power state of the link.

2. The non-transitory machine-readable medium of claim 1 , wherein the first power state of the link comprises a power save state.

3. The non-transitory machine-readable medium of claim 2 , wherein the second power state of the link comprises a power on state.

4. The non-transitory machine-readable medium of claim 1 , wherein the at least one component comprises a first device and the another device coupled to the link comprises a second different device, the second different device located on the SoC.

5. The non-transitory machine-readable medium of claim 1 , wherein to identify the second power state of the platform includes to identify a predefined operation mode of the at least one component.

6. The non-transitory machine-readable medium of claim 5 , wherein to identify the second power state of the link is based on the identified predefined operation mode of the at least one component.

7. The non-transitory machine-readable medium of claim 5 , wherein the identified predefined operation mode of the at least one component comprises an active condition.

8. The non-transitory machine-readable medium of claim 1 , wherein the link is a Peripheral Component Interconnect Express (PCIe) link.

9. The non-transitory machine-readable medium of claim 1 , wherein the first power state is associated with link reduction, and wherein the second power state corresponds to a greater number of active lanes than the first power state.

10. An electronic apparatus comprising:
first logic, at least a portion of which is hardware, to identify a condition of a platform including at least one component of a system on chip (SoC) and further including I/O devices located externally from the SoC, wherein the at least one component is located on the SoC, wherein the first logic to identify the condition includes at least one of the first logic to identify a first power state of the platform and the first logic to identify a second power state of the platform, wherein the second power state is greater than the first power state; and
second logic, at least a portion of which is hardware, to determine a first power state of a link in response to a request for a specific link state, the request originating from one of the I/O devices of the platform, the second logic to determine the first power state of the link based only on identification of the first power state of the platform, the second logic to determine a second power state of the link in response to the request for the specific link state, the second logic to determine the second power state of the link based only on identification of the second power state of the platform, wherein the second power state of the link is greater than the first power state of the link.

11. The electronic apparatus of claim 10 , wherein the first power state of the link comprises a power save state.

12. The electronic apparatus of claim 11 , wherein the second power state of the link comprises a power on state.

13. The electronic apparatus of claim 12 , wherein the first logic to identify the second power state of the platform comprises the first logic to identify an active condition of the at least one component.

14. The electronic apparatus of claim 13 , wherein the second power state of the link is determined based on the identified active condition of the at least one component.

15. The electronic apparatus of claim 10 , wherein the link is a Peripheral Component Interconnect Express (PCIe) link.

16. The electronic apparatus of claim 10 , wherein the at least one component comprises a component of a Platform Controller Hub (PCH) located on the SoC.

17. The electronic apparatus of claim 10 , wherein the at least one component comprises a graphics component located on the SoC.

18. The electronic apparatus of claim 10 , wherein the at least one component comprises a processor of the SoC.

19. The electronic apparatus of claim 10 , wherein the at least one component comprises an I/O controller of the SoC.

20. An apparatus, comprising:
a power supply;
a system on chip (SoC) coupled to one or more downstream devices via one or more links, respectively, the one or more links powered by the power supply;
one or more I/O devices located externally to the SoC; and
a module to:
identify a condition of a platform including the one or more I/O devices located externally from the SoC and further including at least one component of the SoC, wherein the at least one component is located on the SoC, wherein identify the condition includes at least one of identify a first power state of the platform and identify a second power state of the platform, wherein the second power state is greater than the first power state;
determine a power on state of a link of the one or more links in response to a request for a specific link state, the request originating from an I/O device of the one or more I/O devices, wherein the determine the power on state of the link includes determine the power on state of the link based only on identification of the first power state of the platform; and
determine a power save state of the link of the one or more links in response to the request, including determine the power save state of the link based only on identification of the second power state of the platform.

21. The apparatus of claim 20 , wherein the at least one component comprises a first device, and wherein at least one of the one or more downstream devices comprises a second different device, the second different device located on the SoC.

Assignees

• Intel Corp

Inventors

• Gough Corey D
• Steiner Ian M
• Sistla Krishnakanth V

Classifications

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F1/3253

  Power saving in bus · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title