Method of filling through-holes to reduce voids and other defects

Patent metadata

Field	Value
Publication number	US-10508357-B2
Application number	US-201615384681-A
Country	US
Kind code	B2
Filing date	Dec 20, 2016
Priority date	Feb 15, 2016
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

Direct current plating methods inhibit void formation, reduce dimples and eliminate nodules. The method involves electroplating copper at a high current density followed by a pause in electroplating and then turning on the current to electroplate at a lower current density to fill through-holes.

First claim

What is claimed is:

1. A method comprising:
a) providing a printed circuit board with a plurality of through-holes comprising a layer of electroless copper, copper flash or combinations thereof on a surface of the printed circuit board and walls of the plurality of through-holes, wherein the through-holes have diameters of 75-125 μm and wherein the printed circuit board is 200 μm to 300 μm thick;
b) immersing the printed circuit board in a copper electroplating bath comprising an anode; and
c) filling the through-holes with copper by a direct current cycle consisting of applying direct current and a first current density for a first predetermined period of time, wherein the first current density ranges from 1 ASD to 5 ASD, followed by turning off the direct current and the first current density for a second predetermined period of time, wherein the second predetermined period of time is from 0.5 minutes to 10 minutes, and then turning on the direct current and applying a lower second current density for a third predetermined period of time, wherein the lower second current density ranges from 0.5 ASD to 3 ASD and wherein the first current density is higher than the lower second current density and the first predetermined period of time is shorter than the third predetermined period of time in the direct current cycle.

2. The method of claim 1 , wherein the first current density ranges from 1.5 ASD to 4 ASD.

3. The method of claim 1 , wherein the lower second current density ranges from 0.5 ASD to 2 ASD.

4. The method of claim 1 , wherein the first predetermined time period is from 5 minutes to 30 minutes.

5. The method of claim 1 , wherein the third predetermined time period is from 60 minutes to 200 minutes.

Assignees

• Rohm & Haas Elect Mat

Inventors

• Jayaraju Nagarajan
• Barstad Leon
• Niazimbetova Zuhra
• Dziewiszek Joanna

Classifications

• H05K2203/072

  Electroless plating, e.g. finish plating or initial plating · CPC title

• H05K3/423 Primary

  characterised by electroplating method · CPC title

• C25D7/123

  Semiconductors first coated with a seed layer or a conductive layer · CPC title

• C25D5/18

  Electroplating using modulated, pulsed or reversing current · CPC title

• C23C18/1653

  Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating · CPC title