Method of fabricating organic light-emitting display device including substrate having plurality of trenches

Patent metadata

Field	Value
Publication number	US-10504985-B2
Application number	US-201816043125-A
Country	US
Kind code	B2
Filing date	Jul 23, 2018
Priority date	Dec 29, 2015
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

An organic light-emitting display device and a method of fabricating the same are provided. The organic light-emitting display device includes a substrate having a plurality of trenches; a thin film transistor on the substrate; a light-emitting diode connected to the thin film transistor; an upper auxiliary electrode connected to one of an anode and a cathode of the light-emitting diode; and a lower auxiliary electrode in an auxiliary electrode trench among the plurality of trenches of the substrate and connected to the upper auxiliary electrode.

First claim

What is claimed is:

1. A method of fabricating an organic light-emitting display device, the method comprising:
forming a plurality of trenches in a substrate;
disposing a lower auxiliary electrode in one of the plurality of trenches;
forming a light shielding layer simultaneously with the forming of the lower auxiliary electrode, the light shielding layer being embedded in a light shielding trench among the plurality of trenches of the substrate;
forming a thin film transistor on the substrate, the thin film transistor overlapping with the light shielding layer;
forming an anode connected to the thin film transistor and an upper auxiliary electrode connected to the lower auxiliary electrode;
forming an organic light-emitting layer on the anode; and
forming a cathode on the organic light-emitting layer.

2. The method according to claim 1 ,
wherein the forming of the plurality of trenches includes:
forming a photoresist pattern on the substrate; and
forming the trenches by etching the substrate using the photoresist pattern, and

wherein the disposing the lower auxiliary electrode includes:
depositing a seed metal throughout a surface of the substrate and on a surface of the remaining photoresist pattern;
removing the photoresist pattern and the seed metal on the photoresist pattern; and
forming the lower auxiliary electrode in the one of the trenches and an alignment key in a second one of the plurality of trenches by growing the remaining seed metal.

3. The method according to claim 1 ,
wherein the forming of the plurality of trenches and the disposing the lower auxiliary electrode includes:
forming an opaque metal layer on the substrate and a multi-stepped photoresist pattern on the opaque metal layer;
forming the trenches by etching the substrate and the opaque metal layer using the multi-stepped photoresist pattern;
asking the multi-stepped photoresist pattern so that a thicker portion thereof remains;
forming an alignment key by etching the opaque metal layer using the remaining photoresist pattern; and
forming the lower auxiliary electrode in the one of the plurality of the trenches formed in the substrate in which the alignment key has been formed.

4. The method according to claim 2 , further comprising:
forming a first buffer layer on the substrate, the light shielding layer, the lower auxiliary electrode, and the alignment key;
forming a heat resistant buffer layer and a second buffer layer on the first buffer layer such that respective portions of the heat resistant buffer layer and a second buffer are simultaneously formed over the light shielding layer and the lower auxiliary electrode;
forming a semiconductor layer, a gate insulator pattern, and a gate electrode on the portion of the second buffer layer over the light shielding layer;
forming an interlayer insulator film on the gate electrode; and
forming source and drain electrodes in contact with the semiconductor layer with the gate insulator therebetween and simultaneously forming a signal link on the interlayer insulator film at a portion over the heat resistant buffer layer and a second buffer formed over the lower auxiliary electrode, and
wherein the light shielding layer is formed in the light shielding trench among the plurality of trenches to overlap an area having the thin film transistor.

5. The method according to claim 3 , further comprising:
forming a first buffer layer on the substrate, the light shielding layer, the lower auxiliary electrode, and the alignment key;
forming a heat resistant buffer layer and a second buffer layer on the first buffer layer such that respective portions of the heat resistant buffer layer and the second buffer are simultaneously formed over the light shielding layer and the lower auxiliary electrode;
forming a semiconductor layer, a gate insulator pattern, and a gate electrode on the portion of the second buffer layer over the light shielding layer;
forming an interlayer insulator film on the gate electrode; and
forming source and drain electrodes in contact with the semiconductor layer with the gate insulator therebetween and simultaneously forming a signal link on the interlayer insulator film at a portion over the heat resistant buffer layer and a second buffer formed over the lower auxiliary electrode, and
wherein the light shielding layer is formed in the light shielding trench among the plurality of trenches to overlap an area having the thin film transistor.

6. The method according to claim 1 , further comprising forming a buffer layer on the substrate.

7. The method according to claim 1 , wherein a lower pad electrode is embedded in another one of the plurality of trenches, and the method further includes connecting an upper pad electrode to the lower pad electrode through the buffer layer.

Assignees

• Lg Display Co Ltd

Inventors

• Nam Kyoung-Jin
• Kim Jeong-Oh
• Kim Yong-Min
• Park Eun-Young

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H01L27/1225

  Electricity · mapped topic

• H01L23/544

  Electricity · mapped topic

• H01L27/3276

  Electricity · mapped topic