Electrostatic discharge guard ring with snapback protection

Patent metadata

Field	Value
Publication number	US-10504885-B2
Application number	US-201916423754-A
Country	US
Kind code	B2
Filing date	May 28, 2019
Priority date	Oct 12, 2016
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a semiconductor substrate having a first conductivity type and a top surface defining a circuit region and a peripheral region laterally surrounding the circuit region;
a buried layer under the top surface and positioned within the circuit region and adjacent to the peripheral region, the buried layer having a second conductivity type opposite to the first conductivity type; and
a peripheral structure positioned within the peripheral region and adjacent to the top surface, the peripheral structure including:
a first contact region having the first conductivity type;
a second contact region having the second conductivity type, the second contact region interposed between the buried layer and the first contact region;
a second buried layer having the second conductivity type, the second buried layer extending under the first contact region and the second contact region; and
a doped region having the first conductivity type and a higher doping concentration than the semiconductor substrate, the doped region extending from the first contact region to the second buried layer.

2. The integrated circuit of claim 1 , further comprising:
a bipolar transistor structure having:
a collector region in the buried layer;
a base region extending from the first contact region to a portion of the semiconductor substrate interposed between the second contact region and the buried layer; and
an emitter region in the second contact region.

3. The integrated circuit of claim 1 , wherein each of the first and second contact regions extends contiguously within the peripheral region and laterally surrounds the circuit region.

4. The integrated circuit of claim 1 , wherein each of the first and second contact regions is segmented within the peripheral region and laterally surrounds the circuit region.

5. The integrated circuit of claim 1 , wherein the peripheral structure includes:
a doped region having the first conductivity type and a higher doping concentration than the semiconductor substrate, the doped region interposed between the second contact region and the buried layer.

6. The integrated circuit of claim 1 , further comprising:
a lateral drain metal oxide semiconductor (LDMOS) transistor within the circuit region, the LDMOS transistor having:
a drain contact region adjacent to the top surface;
a first doped region having the second conductivity type and extending from the drain contact region to the buried layer;
a source contact region positioned between the peripheral structure and the drain contact region; and
a second doped region having the second conductivity type and extending from the buried layer to the top surface adjacent to the source contact region.

7. The integrated circuit of claim 1 , further comprising:
a diode having:
a cathode contact region within the circuit region and adjacent to the top surface;
a doped region having the second conductivity type and extending from the cathode contact region to the buried layer; and
an anode region extending from the first contact region to a portion of the semiconductor substrate interposed between the second contact region and the buried layer.

8. The integrated circuit of claim 1 , further comprising:
a first electrode configured to receive a voltage above 1 kV;
a doped region having the second conductivity type and establishing a discharge path between the first electrode and the buried layer; and
a second electrode configured to receive a ground supply voltage, and the second electrode coupled to the first contact region and the second contact region to extend the discharge path.

9. The integrated circuit of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.

10. An integrated circuit, comprising:
a semiconductor substrate having a P-type dopant and a top surface defining a circuit region and a peripheral region laterally surrounding the circuit region;
a diode having a cathode region positioned within the circuit region and adjacent to the peripheral region, the cathode region having an N-type dopant;
a lateral drain metal oxide semiconductor (LDMOS) transistor positioned within the circuit region and adjacent to the peripheral region, the LDMOS transistor having a lateral drain region separated from the cathode region, and the lateral drain region having the N-type dopant; and
a peripheral structure positioned within the peripheral region and adjacent to the top surface, the peripheral structure including:
a first contact region having the P-type dopant;
a second contact region having the N-type dopant, the second contact region interposed between the first contact region and the cathode region, and interposed between the first contact region and the lateral drain region;
a buried layer having the N-type dopant, the buried layer extending under the first contact region and the second contact region; and
a doped region having the P-type dopant and a higher doping concentration than the semiconductor substrate, the doped region extending from the first contact region to the buried layer.

11. The integrated circuit of claim 10 , further comprising:
a bipolar transistor structure having:
a collector region in the cathode region;
a base region extending from the first contact region to a portion of the semiconductor substrate interposed between the second contact region and the cathode region; and
an emitter region in the second contact region.

12. The integrated circuit of claim 10 , further comprising:
a bipolar transistor structure having:
a collector region in the lateral drain region;
a base region extending from the first contact region to a portion of the semiconductor substrate interposed between the second contact region and the lateral drain region; and
an emitter region in the second contact region.

13. The integrated circuit of claim 10 , wherein each of the first and second contact regions extends contiguously within the peripheral region and laterally surrounds the circuit region.

14. The integrated circuit of claim 10 , wherein each of the first and second contact regions is segmented within the peripheral region based on a distribution of the diode and the LDMOS transistor.

15. The integrated circuit of claim 10 , wherein the peripheral structure includes:
a doped region having the P-type dopant and a higher doping concentration than the semiconductor substrate, the doped region interposed between the second contact region and the cathode region of the diode, and interposed between the second contact region and the LDMOS transistor.

16. The integrated circuit of claim 10 , wherein the LDMOS transistor includes:
a drain contact region adjacent to the top surface;
a first doped region having the N-type dopant and extending from the drain contact region to the lateral drain region;
a source contact region positioned between the peripheral structure and the drain contact region; and
a second doped region having the N-type dopant and extending from the lateral drain region to the top surface adjacent to the source contact region.

17. The integrated circuit of claim 10 , wherein the diode includes:
a cathode contact region within the circuit region and adjacent to the top surface;
a doped region having the N-type dopant and extending from the cathode contact region to the cathode region; and
an anode region extending from the first contact region to a portion of the semiconductor substrate interposed between the second contact region and th

Assignees

• Texas Instruments Inc

Inventors

• Kim Sunglyong
• LaFonteese David
• Sridhar Seetharaman
• Pendharkar Sameer

Classifications

• H01L29/1095

  Electricity · mapped topic

• H01L27/0259 Primary

  Electricity · mapped topic

• H01L29/0619

  Electricity · mapped topic

• H01L29/7818

  Electricity · mapped topic

• H10D64/111

  Field plates · CPC title