Time to digital converter with increased range and sensitivity

Patent metadata

Field	Value
Publication number	US-10503122-B2
Application number	US-201816167488-A
Country	US
Kind code	B2
Filing date	Oct 22, 2018
Priority date	Apr 14, 2017
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency.

First claim

What is claimed:

1. A method comprising:
receiving, at a receive phase-to-digital conversion (PDC) circuit, a modulated signal having a carrier frequency;
obtaining a phase measurement between the modulated signal and a local clock signal;
generating a carrier-based phase correction value by accumulating a phase-correction increment;
generating a corrected phase measurement value based on a difference between the phase measurement and the carrier-based phase correction value; and
generating a carrier phase measurement by scaling the corrected phase measurement value.

2. The method of claim 1 , wherein generating the phase-correction increment is based on (i) a count of periods of the modulated signal occurring between each generation of a corrected phase measurement, and (ii) a difference between the carrier frequency and a frequency of the local clock signal.

3. The method of claim 2 , wherein generating the carrier-based phase correction value is inhibited if a rising edge of the modulated signal does not occur within a timing window.

4. The method of claim 1 , wherein obtaining the phase measurement comprises:
determining a coarse measurement by determining a phase interval of a plurality of phase intervals of the local clock that coincides with a rising edge of the modulated signal;
determining a fine measurement error of the coarse measurement; and
determining the phase measurement by combining the coarse measurement and the fine measurement error.

5. The method of claim 4 , wherein combining the coarse measurement and the fine measurement further comprises:
scaling the coarse measurement by a coarse measurement scaling factor; and
scaling the fine measurement error by a fine measurement scaling factor.

6. The method of claim 5 ,
wherein scaling the coarse measurement converts the coarse measurement from an index of the phase interval to a phase angle value, and
wherein scaling the fine measurement converts the fine measurement error from a time value to phase with respect to the local clock signal.

7. The method of claim 4 , wherein determining the phase interval is determined according to a state of a plurality of ring oscillator elements.

8. The method of claim 7 , wherein determining the fine measurement error comprises:
injecting, into a slow line of two-dimensional Vernier delay elements, a rising edge of the modulated signal;
injecting, into a fast line of two-dimensional Vernier delay elements, an output of the ring oscillator associated with the determined phase interval; and
determining a fine measurement error using a matrix of arbiters connected between the slow line and fast line.

9. The method of claim 1 , wherein generating the carrier phase measurement comprises scaling the corrected phase measurement by a multiple of a ratio of the carrier frequency to the frequency of the local clock signal.

10. The method of claim 1 , further comprising preprocessing the modulated signal by reducing the frequency using a harmonic injection ILO.

11. The method of claim 1 , further comprising preprocessing the modulated signal by reducing the frequency using a divider circuit.

12. The method of claim 1 , further comprising preprocessing the modulated signal by reducing the frequency using a mixer circuit.

13. An apparatus comprising:
an analog receiver circuit configured to receive a modulated signal having a carrier frequency;
a phase-to-digital conversion (PDC) circuit coupled to the analog receiver circuit and configured to obtain a phase measurement between the modulated signal and a local clock signal;
a carrier-based phase correction circuit coupled to the PDC circuit and configured to generate a carrier-based phase correction value by accumulating a phase-correction increment;
a corrected phase measurement circuit coupled to the carrier-based phase correction circuit and configured to generate a corrected phase measurement value based on a difference between the phase measurement and the carrier-based phase correction value; and
a carrier phase measurement circuit coupled to the corrected phase measurement circuit and configured to generate a carrier phase measurement by scaling the corrected phase measurement value.

14. The apparatus of claim 13 , wherein the carrier-based phase correction circuit comprises a lookup table.

15. The apparatus of claim 13 , wherein the phase-correction increment is based on (i) a count of periods of the modulated signal occurring between each generation of a corrected phase measurement, and (ii) a difference between the carrier frequency and a frequency of the local clock signal.

16. The apparatus of claim 15 , wherein the count of periods of the modulated signal is used to control a multiplexer to select a table entry storing a multiple of a single period carrier offset value.

17. The apparatus of claim 15 , further comprising an overflow circuit coupled to the corrected phase measurement circuit and configured to inhibit generating the carrier-based phase correction value if a rising edge of the modulated signal does not occur within a timing window.

18. The apparatus of claim 13 , wherein the PDC circuit comprises:
a coarse measurement circuit configured to determine a coarse measurement by determining a phase interval of a plurality of phase intervals of the local clock that coincides with a rising edge of the modulated signal;
a fine measurement error circuit coupled to the coarse measurement circuit and configured to determine a fine measurement error of the coarse measurement; and
a phase measurement circuit coupled to the fine measurement circuit and configured to determine the phase measurement by combining the coarse measurement and the fine measurement error.

19. The apparatus of claim 18 , further comprising:
a coarse measurement scaling circuit coupled to the coarse measurement circuit and configured to scale the coarse measurement by a coarse measurement scaling factor; and
a fine measurement scaling circuit coupled to the fine measurement error circuit and configured to scale the fine measurement error by a fine measurement scaling factor.

20. The apparatus of claim 19 ,
wherein the coarse measurement scaling circuit uses the coarse measurement scaling factor to convert the coarse measurement from an index of the phase interval to a phase value, and
wherein the fine measurement scaling circuit uses the fine measurement scaling factor to convert the fine measurement error from a time value to phase with respect to the local clock signal.

21. The apparatus of claim 18 , wherein the coarse measurement circuit comprises a plurality of ring oscillator elements.

22. The apparatus of claim 18 , wherein the fine measurement error circuit comprises:
a first set of one or more inverters forming a first line of delay elements;
a second set of one or more inverters forming a second line of delay elements, wherein the first line of delay elements is slower than the second line of delay elements;
a matrix of latches equal to the number of inverters in the first line of delay elements times the number of inverters in the second line of delay elements;
a set of connections that connect each inverter output in the first line of delay elements to each first latch input in a column of the matrix of latches; and
a set of connections that connect each inverter output in the second line of delay elements to each second latch input in a row of the matrix of latches.

23. The a

Assignees

• Innophase Inc

Inventors

• Testi Nicolo

Classifications

• G04F10/06

  by measuring phase {(G04F10/005 takes precedence)} · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03L7/0997

  Controlling the number of delay elements connected in series in the ring oscillator · CPC title

• H04L27/2272

  using phase locked loops (H04L27/2273 takes precedence) · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title