Communication system with frequency synthesis mechanism and method of operation thereof

Patent metadata

Field	Value
Publication number	US-9240914-B2
Application number	US-201414152617-A
Country	US
Kind code	B2
Filing date	Jan 10, 2014
Priority date	Jan 15, 2013
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A communication system includes: a frequency synthesizer, configured to reference a radio frequency (RF) signal, in a device including: a ring oscillator with track-and-hold circuit electrically connected to a reference clock, a bank of comparators, electrically connected to the ring oscillator with track-and-hold circuit, configured to measure a coarse timing, and an analog-to-digital converter, electrically connected to the ring oscillator with track-and-hold circuit, configured to generate a fine timing; a communication interface, electrically connected to the frequency synthesizer, is configured to receive a device transmission; and a control unit, electrically connected to the communication interface, is configured to display a receiver data from the a radio frequency (RF) signal.

First claim

What is claimed is:

1. A communication system comprising:
a frequency synthesizer, configured to reference a radio frequency (RF) signal, including:
a ring oscillator with track-and-hold circuit electrically connected to a reference clock,
a bank of comparators, electrically connected to the ring oscillator with track-and-hold circuit, configured to measure a coarse timing from the reference clock, and
an analog-to-digital converter, electrically connected to the ring oscillator with track-and-hold circuit, configured to generate a fine timing;

a communication interface, electrically connected to the frequency synthesizer, configured to receive a device transmission; and
a control unit, electrically connected to the communication interface, configured to display a receiver data from the a radio frequency (RF) signal.

2. The system as claimed in claim 1 wherein the ring oscillator with track-and-hold circuit includes an interpolated delay cell comprising two or more of a multi-input inverter with track-and-hold circuit.

3. The system as claimed in claim 1 wherein the bank of comparators includes a coarse encoder electrically connected to the ring oscillator with track-and-hold circuit for generating a cycle count.

4. The system as claimed in claim 1 wherein the analog-to-digital converter includes a feedback capacitor adjacent to the ring oscillator with track-and-hold circuit.

5. The system as claimed in claim 1 wherein the analog-to-digital converter includes an offset compensated comparator for selecting a partial transition in the ring oscillator with track-and-hold circuit.

6. The system as claimed in claim 1 wherein the frequency synthesizer includes a clock buffer, electrically connected to the ring oscillator with track-and-hold circuit, configured to clock a counter for determining a zone identification.

7. The system as claimed in claim 1 wherein the frequency synthesizer includes an analog-to-digital converter (ADC) gain tracking circuit electrically connected to an ADC adjust multiplier.

8. The system as claimed in claim 1 wherein the frequency synthesizer includes a time-to-digital converter (TDC) gain tracking circuit electrically connected to a TDC adjust multiplier.

9. The system as claimed in claim 1 wherein the frequency synthesizer includes a digitally controlled oscillator (DCO) configured to receive a coded measured timing through a loop filter.

10. The system as claimed in claim 1 wherein the ring oscillator with track-and-hold circuit includes a holding capacitor electrically connected to an resistively degenerated buffer controlled by an enable buffer line configured to generate a voltage input line.

11. A method of operation of a communication system comprising:
synthesizing an output frequency, in a device, for referencing a radio frequency (RF) signal including:
enabling a ring oscillator with track-and-hold circuit by a reference clock,
accessing a bank of comparators for measuring a coarse timing from the reference clock, and
generating a fine timing by enabling an analog-to-digital converter (ADC) electrically connected to the ring oscillator with track-and-hold circuit;

receiving a device transmission by referencing a communication interface with the output frequency; and
displaying a receiver data, from the radio frequency (RF) signal, by a control unit.

12. The method as claimed in claim 11 wherein synthesizing the output frequency includes switching an interpolated delay cell comprising two or more of a multi-input inverter with track-and-hold circuit.

13. The method as claimed in claim 11 wherein measuring the coarse timing includes generating a cycle count.

14. The method as claimed in claim 11 wherein generating the fine timing includes charging a feedback capacitor by the ring oscillator with track-and-hold circuit.

15. The method as claimed in claim 11 wherein generating the fine timing includes selecting a partial transition.

16. The method as claimed in claim 11 wherein measuring the coarse timing includes determining a zone identification.

17. The method as claimed in claim 11 wherein synthesizing the output frequency includes scaling the fine timing by an ADC adjust multiplier.

18. The method as claimed in claim 11 wherein synthesizing the output frequency includes scaling the coarse timing by a time-to-digital converter (TDC) adjust multiplier.

19. The method as claimed in claim 11 wherein synthesizing the output frequency includes receiving a coded measured timing by a digitally controlled oscillator (DCO).

20. The method as claimed in claim 11 wherein enabling the ring oscillator with track-and-hold circuit includes charging a holding capacitor for generating a voltage input line.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yao Chih-Wei

Classifications

• H04L27/0014 Primary

  Carrier regulation (of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657) · CPC title

• H04L2027/0016

  Stabilisation of local oscillators · CPC title

• H04L2027/0069

  Loop filters · CPC title