Progressive effort decoder architecture

Patent metadata

Field	Value
Publication number	US-9654144-B2
Application number	US-201414502513-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Sep 30, 2014
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. The processor may receive the codeword and determine whether the codeword is independently decodable using a BCH decoder. The processor may then decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder. Otherwise, the processor may decode the codeword using a second decoder and the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder.

First claim

What is claimed is:

1. A method, comprising:
receiving, via a processor, a codeword configured to indicate whether data associated with the codeword includes one or more errors;
determining whether the codeword is independently decodable using a first error correction code (ECC) algorithm;
decoding the codeword using the first ECC algorithm when the codeword is determined to be independently decodable by the first ECC algorithm; and
decoding the codeword using the first ECC algorithm in combination with a second ECC algorithm when the codeword is not determined to be independently decodable by the first ECC algorithm alone, wherein a portion of the codeword is decoded using the second ECC algorithm and a remaining portion of the codeword is decoded using the first ECC algorithm.

2. The method of claim 1 , wherein the codeword is independently decodable by the first ECC algorithm when the data is written into a memory during an initial-life of the memory.

3. The method of claim 1 , wherein the codeword is not independently decodable by the first ECC algorithm when a raw bit error rate value associated with the data is more than a first value.

4. The method of claim 1 , wherein decoding the codeword using the first ECC algorithm in combination with the second ECC algorithm comprises:
decoding the portion of the codeword at least partially using the second ECC algorithm, thereby generating a partially decoded codeword;
determining whether the partially decoded codeword is decodable using the first ECC algorithm;
decoding the remaining portion of the codeword using the first ECC algorithm in combination with the second ECC algorithm when the partially decoded codeword is determined to be decodable by the first ECC algorithm; and
decoding a second portion of the codeword using a third ECC algorithm in and a second remaining portion of the codeword using the first ECC algorithm when the partially decoded codeword is not determined to be decodable by the first ECC algorithm in combination with the second ECC algorithm.

5. The method of claim 1 , comprising storing soft data associated with the decoding of the codeword in a cache.

6. The method of claim 1 , wherein the codeword is received by directly accessing one or more memory cells of the memory via a hard read.

7. The method of claim 6 , wherein the hard read comprises multiple channels.

8. A memory device, comprising;
one or more memory components configured to store data;
a processor configured to decode a codeword associated with the data, wherein the processor is configured to:
receive the codeword;
determine whether the codeword is independently decodable using a BCH decoder;
decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder; and

decode a portion of the codeword using a second decoder and decode a remaining portion of the codeword using the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder by itself.

9. The memory device of claim 8 , wherein the memory components comprise one or more NAND memory cells.

10. The memory device of claim 8 , wherein the memory components are configured to employ at least one program/erase cycle when writing the data.

11. The memory device of claim 8 , wherein the second decoder corresponds to a low density parity check (LDPC) code.

12. The memory device of claim 8 , wherein the second decoder is configured to consume more energy as compared to the BCH decoder.

13. The memory device of claim 8 , wherein the second decoder is configured to perform more than one iteration.

14. The memory device of claim 8 , wherein the processor is configured to determine whether the codeword is decodable using the BCH decoder based on a Berlekamp algorithm.

15. The memory device of claim 8 , wherein the BCH decoder is configured to send a status update regarding whether the codeword is decodable using the BCH decoder to a cache.

16. The memory device of claim 15 , wherein the BCH decoder is configured to send the status update via a Progressive Side-band Information (PSI) component.

17. A tangible, non-transitory, machine-readable medium, comprising instructions when executed by a processor configured to:
receive a codeword configured to indicate whether data associated with the codeword includes one or more errors;
determine whether the codeword is independently decodable using a BCH decoder;
decode the codeword using the BCH decoder when the codeword is determined to be independently decodable by the BCH decoder; and
decode a first portion of the codeword using a first low density parity check (LDPC) decoder and a first remaining portion of the codeword using the BCH decoder or decode a second portion of the codeword using a second LDPC decoder and a second remaining portion of the codeword using the BCH decoder when the codeword is not determined to be independently decodable by the BCH decoder alone.

18. The tangible, non-transitory, machine-readable medium of claim 17 , wherein the instructions are configured to decode the first remaining portion of the codeword using the BCH decoder and the first portion of the codeword using the first LDPC decoder after determining that the codeword is not independently decodable using the BCH decoder alone.

19. The tangible, non-transitory, machine-readable medium of claim 17 , wherein the instructions are configured to decode the second remaining portion of the codeword using the BCH decoder and the second portion of the codeword using the second LDPC decoder after determining that the codeword is not decodable using the BCH decoder in combination with the first LDPC decoder.

20. The tangible, non-transitory, machine-readable medium of claim 19 , wherein the instructions are configured to decode the second remaining portion of the codeword using the BCH decoder and the second portion of the codeword using the second LDPC decoder and soft data regarding a reliability of each bit in the codeword when the second remaining portion of the codeword is not decodable by the BCH decoder and the second portion of the codeword is not decodable by the second LDPC decoder.

21. The tangible, non-transitory, machine-readable medium of claim 20 , wherein the BCH decoder is configured to decode the second remaining portion of the codeword and the second LDPC decoder is configured to decode the second portion of the codeword using only hard data.

22. The tangible, non-transitory, machine-readable medium of claim 20 , wherein the second LDPC decoder is configured to consume more energy as compared to the first LDPC decoder.

23. The tangible, non-transitory, machine-readable medium of claim 20 , wherein the second LDPC decoder is configured to detect more errors as compared to the first LDPC decoder.

24. The tangible, non-transitory, machine-readable medium of claim 17 , wherein the first and second LDPC decoders are implemented using a scalable LDPC code decoder, wherein the scalable LDPC code decoder is configured to adjust a decoder precision for each respective LDPC decoder, a number of decoder iterations for each respective LDPC decoder, or any combination thereof.

25. The tangible, non-transitory, machine-readable medium of claim 17 , wherein the first and second LDPC decoders are associated with separate hardware components.

26. The tangible, non-transitory, machine-r

Assignees

• Micron Technology Inc

Inventors

• Parthasarathy Sivagnanam
• Richardson Nicholas Julian
• Khayat Patrick Robert
• Kaynak Mustafa Nazmi
• Ling Ka Leung
• Eisenhuth Robert B

Classifications

• H03M13/2906

  using block codes (H03M13/2957 takes precedence) · CPC title

• H03M13/3715

  Adaptation to the number of estimated errors or to the channel state · CPC title

• H03M13/1111

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title

• H03M13/152 Primary

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• H03M13/2927 Primary

  Decoding strategies · CPC title