Optoelectronic device comprising a light-emitting component and a transistor

Patent metadata

Field	Value
Publication number	US-10497743-B2
Application number	US-201615781085-A
Country	US
Kind code	B2
Filing date	Dec 1, 2016
Priority date	Dec 3, 2015
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

An optoelectronic device including a light emitting component and a field-effect transistor, the optoelectronic device including a first semiconductor layer made of a III-V or II-VI compound doped a first conductivity type; an active layer of the light-emitting component; and a second semiconductor layer made of the III-V or III-VI compound doped a second conductivity type opposite the first type, the active layer being sandwiched between the first and second semiconductor layers, wherein the channel of the field-effect transistor is located in the first semiconductor layer, the first semiconductor layer being uninterrupted between the field-effect transistor and the lightemitting component.

First claim

The invention claimed is:

1. An optoelectronic device comprising a light-emitting component and a field-effect transistor, the optoelectronic device comprising:
a first doped semiconductor layer of a III-V or II-VI compound, of a first conductivity type;
an active layer of the light-emitting component;
a second doped semiconductor layer of the III-V or II-VI compound, of a second conductivity type opposite to the first conductivity type, the active layer being sandwiched between the first and second doped semiconductor layers,
wherein a channel of the field-effect transistor is located in the first doped semiconductor layer, the first doped semiconductor layer being uninterrupted between the field-effect transistor and the light-emitting component, and
the optoelectronic device further comprising a first trench successively crossing at least the second doped semiconductor layer, the active layer, and a portion only of the first doped semiconductor layer, and containing a first electrically-conductive core and a first electrically-insulating layer covering walls of the first trench at least directly between the first electrically-conductive core and the second doped semiconductor layer and directly between the first electrically-conductive core and the active layer.

2. The optoelectronic device of claim 1 , wherein the first electrically-insulating layer covers walls of the first trench between the first electrically-conductive core and the first doped semiconductor layer.

3. The optoelectronic device of claim 1 , wherein the first electrically-conductive core is in contact with the first doped semiconductor layer.

4. The optoelectronic device of claim 3 , wherein a work function of a material forming the first electrically-conductive core is greater than 4 eV.

5. The optoelectronic device of claim 1 , further comprising a third doped semiconductor layer of the III-V or II-VI compound, of the first conductivity type, having a dopant concentration greater than a dopant concentration of the first doped semiconductor layer, in contact with the first doped semiconductor layer and interposed between the first doped semiconductor layer and the active layer.

6. The optoelectronic device of claim 5 , comprising a second trench successively crossing at least the second doped semiconductor layer, the active layer, and all or part of the third doped semiconductor layer, and containing a second electrically-conductive core in contact with the third doped semiconductor layer and containing a second electrically-insulating layer covering walls of the second trench at least between the second electrically-conductive core and the second doped semiconductor layer and between the second electrically-conductive core and the active layer.

7. The optoelectronic device of claim 6 , comprising a first electrically-conductive pad in contact with the first electrically-conductive core and a second electrically-conductive pad in contact with the second electrically-conductive core, the first and second electrically-conductive pads resting on a planar surface.

8. The optoelectronic device of claim 1 , wherein the active layer is a layer having most of an electromagnetic radiation supplied by the optoelectronic device emitted therefrom.

9. The optoelectronic device of claim 8 , wherein the active layer comprises a single quantum well or multiple quantum wells.

10. The optoelectronic device of claim 1 , wherein a dopant concentration of the first doped semiconductor layer is in the range from 10 15 atoms/cm 3 to 10 18 atoms/cm 3 .

11. The optoelectronic device of claim 1 , wherein a thickness of the second doped semiconductor layer opposite the first trench is in the range from 50 nm to 150 nm when a dopant concentration of the second doped semiconductor layer is greater than 10 17 atoms/cm 3 .

12. The optoelectronic device of claim 1 , wherein a thickness of the first electrically-conductive core is in the range from 10 times to 50 times a thickness of the first doped semiconductor layer opposite the first trench.

13. A method of manufacturing an optoelectronic device comprising a light-emitting component and a field-effect transistor, the method comprising the successive steps of:
forming a first doped semiconductor layer of a III-V or II-VI compound, of a first conductivity type;
forming an active layer of the light-emitting component;
forming a second doped semiconductor layer of the III-V or II-VI compound, of a second conductivity type opposite to the first conductivity type, the active layer being sandwiched between the first and second doped semiconductor layers;
forming a channel of the field-effect transistor in the first doped semiconductor layer, the first doped semiconductor layer being uninterrupted between the field-effect transistor and the light-emitting component;
forming a first trench successively crossing at least the second doped semiconductor layer, the active layer, and a portion only of the first doped semiconductor layer; and
forming, in the first trench, a first electrically-conductive core and a first electrically-insulating layer covering walls of the first trench at least directly between the first electrically-conductive core and the second doped semiconductor layer and directly between the first electrically-conductive core and the active layer.

14. The method of claim 13 , further comprising the step of forming a third doped semiconductor layer of the III-V or II-VI compound, of the first conductivity type, having a dopant concentration greater than a dopant concentration of the first doped semiconductor layer, in contact with the first doped semiconductor layer and interposed between the first doped semiconductor layer and the active layer.

15. The method of claim 14 , further comprising the steps of:
forming a second trench successively crossing at least the second doped semiconductor layer, the active layer, and a portion only of the third doped semiconductor layer; and
forming, in the second trench, a second electrically-conductive core in contact with the third doped semiconductor layer and a second electrically-insulating layer covering walls of the second trench at least between the second electrically-conductive core and the second doped semiconductor layer and between the second electrically-conductive core and the active layer.

Assignees

• Commissariat A Ienergie Atomique Et Aux Energies Alternatives

Inventors

• Robin Ivan-Christophe
• Bono Hubert
• Bouchet Thierry
• Charles Matthew
• Escoffier René
• Morvan Erwan

Classifications

• H01L33/382

  Electricity · mapped topic

• H01L27/15 Primary

  Electricity · mapped topic

• H10D84/01

  Manufacture or treatment · CPC title

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title