Method of fabricating a microelectronic substrate

Patent metadata

Field	Value
Publication number	US-10494700-B2
Application number	US-201715674184-A
Country	US
Kind code	B2
Filing date	Aug 10, 2017
Priority date	Dec 9, 2014
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.

First claim

What is claimed is:

1. A method of fabricating a microelectronic substrate, comprising:
forming a dielectric layer having first surface;
forming a metallization layer on the dielectric layer first surface;
contacting the metallization layer with an electrodeposition solution; and
forming a graded copper alloy layer from the metallization layer by inducing and varying an electrical potential between the electrodeposition solution and the dielectric layer, wherein the graded copper alloy layer comprises copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof.

2. The method of claim 1 wherein forming the graded copper alloy layer comprises forming the graded copper alloy layer having between about 90% and 100% copper proximate one of the graded copper alloy layer first surface and the graded copper alloy layer second surface, and between about 0% and 10% copper proximate the other of the graded copper alloy layer first surface and the graded copper alloy layer second surface.

3. The method of claim 1 , wherein forming the graded copper alloy layer comprises forming the grade copper alloy layer having a concentration of copper proximate one of the graded copper alloy layer first surface and the graded copper alloy second surface between about 90% and 100% and the remainder being the alloying metal and the co-deposition metal, wherein the co-deposition metal has a concentration between about trace levels and 10% and, proximate the other of the graded copper alloy layer first surface and the graded copper alloy layer second surface, a concentration of copper between about 0% and 10% and the remainder being the alloying metal and the co-deposition metal, wherein the co-deposition metal has a concentration between about trace levels and 10%.

4. The method of claim 1 , further comprising etching the graded copper alloy layer to form at least one graded copper alloy conductive route.

5. The method of claim 1 , wherein the copper of the graded copper alloy layer has a substantially linear concentration gradient.

6. A method of fabricating a microelectronic structure, comprising:
forming a microelectronic substrate comprising:
forming a dielectric layer having first surface;
forming a metallization layer on the dielectric layer first surface;
contacting the metallization layer with an electrodeposition solution; and
forming a graded copper alloy layer from the metallization layer by inducing and varying an electrical potential between the electrodeposition solution and the dielectric layer, wherein the copper alloy layer comprises copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof; and

electrically connecting a microelectronic device to the microelectronic substrate.

7. The method of claim 6 , further comprising forming a board and electrically connecting the microelectronic substrate to the board.

8. The method of claim 6 , wherein forming the graded copper alloy layer comprises forming the graded copper alloy layer having between about 90% and 100% copper proximate one of the graded copper alloy layer first surface and the graded copper alloy layer second surface, and between about 0% and 10% copper proximate the other of the graded copper alloy layer first surface and the graded copper alloy layer second surface.

9. The method of claim 6 , wherein forming the graded copper alloy layer comprises forming the grade copper alloy layer having a concentration of copper proximate one of the graded copper alloy layer first surface and the graded copper alloy second surface between about 90% and 100% and the remainder being the alloying metal and the co-deposition metal, wherein the co-deposition metal has a concentration between about trace levels and 10% and, proximate the other of the graded copper alloy layer first surface and the graded copper alloy layer second surface, a concentration of copper between about 0% and 10% and the remainder being the alloying metal and the co-deposition metal, wherein the co-deposition metal has a concentration between about trace levels and 10%.

10. The method of claim 6 , further comprising etching the graded copper alloy layer to form at least one graded copper alloy conductive route.

11. The method of claim 6 , wherein the copper of the graded copper alloy layer has a substantially linear concentration gradient.

Assignees

• Intel Corp

Inventors

• May Robert A
• Boyapati Sri Ranga Sai
• Alur Amruthavalli P
• Sobieski Daniel N

Classifications

• C22C27/04

  Alloys based on tungsten or molybdenum · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title