Horizontal gate all around and FinFET device isolation

Patent metadata

Field	Value
Publication number	US-10490666-B2
Application number	US-201715804691-A
Country	US
Kind code	B2
Filing date	Nov 6, 2017
Priority date	May 11, 2015
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

First claim

What is claimed is:

1. A horizontal gate-all-around device structure, comprising:
a substrate having a superlattice structure formed thereon, the superlattice structure comprising:
a silicon material layer;
a first silicon germanium material layer comprising between about 20% and about 40% germanium; and
a second silicon germanium material layer comprising between about 50% and about 80% germanium, wherein the silicon material layer, the first silicon germanium material layer, and the second silicon germanium layer are disposed in a stacked arrangement; and

a liner formed on sidewalls of the superlattice structure.

2. The device structure of claim 1 , wherein the second silicon germanium material layer is disposed between a plurality of the first silicon germanium material layers.

3. The device structure of claim 1 , wherein the liner is an oxynitride material, a silicon nitride material, or combinations thereof.

4. The device structure of claim 2 , wherein the liner is an oxynitride material, a silicon nitride material, or combinations thereof.

5. The device structure of claim 1 , wherein the first silicon germanium material layer and the second silicon germanium material layer are disposed in an alternating stacked arrangement.

6. The device structure of claim 1 , wherein the silicon material layer has a thickness of between about 5 nm and about 15 nm.

7. The device structure of claim 6 , wherein the first silicon germanium material layer has a thickness of between about 3 nm and about 10 nm.

8. The device structure of claim 7 , wherein the second silicon germanium material layer has a thickness of between about 5 nm and about 15 nm.

9. The device structure of claim 1 , further comprising:
a hardmask disposed on the first silicon germanium material layer.

10. A horizontal gate-all-around device structure, comprising:
a superlattice structure, comprising:
a silicon material layer;
a first silicon germanium material layer comprising between about 20% and about 40% germanium; and
a second silicon germanium material layer comprising between about 50% and about 80% germanium, wherein the silicon material layer, the first silicon germanium material layer, and the second silicon germanium layer are disposed in a stacked arrangement; and

a liner formed on sidewalls of the superlattice structure.

11. The device structure of claim 10 , wherein the second silicon germanium material layer is disposed between a plurality of the first silicon germanium material layers.

12. The device structure of claim 10 ,
wherein the liner is an oxynitride material, a silicon nitride material, or combinations thereof.

13. The device structure of claim 10 , wherein the first silicon germanium material layer and the second silicon germanium material layer are disposed in an alternating stacked arrangement.

14. The device structure of claim 10 , wherein the silicon material layer has a thickness of between about 5 nm and about 15 nm.

15. The device structure of claim 14 , wherein the first silicon germanium material layer has a thickness of between about 3 nm and about 10 nm.

16. The device structure of claim 15 , wherein the second silicon germanium material layer has a thickness of between about 5 nm and about 15 nm.

17. The device structure of claim 10 , further comprising:
a hardmask disposed on the first silicon germanium material layer.

Assignees

• Applied Materials Inc

Inventors

• Sun Shiyu
• Kim Nam Sung
• Yoshida Naomi
• Guarini Theresa Kramer
• Jun Sung Won
• PENA Vanessa
• Sanchez Errol Antonio C
• Colombeau Benjamin
• Chudzik Michael
• Wood Bingxi

Classifications

• H01L29/785 Primary

  Electricity · mapped topic

• H01L29/78642

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L29/1054

  Electricity · mapped topic