Semiconductor device

Patent metadata

Field	Value
Publication number	US-10490486-B2
Application number	US-201816140791-A
Country	US
Kind code	B2
Filing date	Sep 25, 2018
Priority date	Dec 28, 2000
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor chip having a first side, a second side opposite the first side, a first upper surface on which a plurality of electrodes is formed and a first back surface opposite the first upper surface;
a tab having a first side, a second upper surface to which the semiconductor chip is fixed;
a plurality of leads arranged along the first side of the tab in a plan view;
a plurality of first wires connecting a plurality of first electrodes of the plurality of electrodes with the plurality of leads, respectively;
a plurality of second wires connecting a plurality of second electrodes of the plurality of electrodes with the tab, respectively; and
a seal member sealing the semiconductor chip, the tab, a part of each of the plurality of leads, the plurality of first wires and the plurality of second wires,
wherein, in the plan view, the plurality of electrodes of the semiconductor chip is arranged along the first side of the semiconductor chip,
wherein, in the plan view, the first side of the semiconductor chip extends in a first direction and is disposed between the second side of the semiconductor chip and the first side of the tab,
wherein, in the plan view, the first side of the tab extends along the first side of the semiconductor chip,
wherein, in the plan view, the first side of the tab is located between the first side of the semiconductor chip and the plurality of leads,
wherein, in the plan view, the tab has a slit that pierces the tab, and that is formed between the first side of the semiconductor chip and the first side of the tab,
wherein, in the plan view, the slit has a central portion extending in the first direction, the central portion having a first width that is a length extending in a second direction crossing the first direction, and the slit has at least one end portion having a second width that is a length extending in the second direction, and wherein the first width is less than the second width,
wherein, in the plan view, a wire connecting portion of each of the plurality of second wires, which is connected to the tab, is located between the slit and the first side of the tab, and
wherein, in the plan view, each of the plurality of second wires intersects with the slit.

2. The semiconductor device according to claim 1 ,
wherein, in the plan view, the slit has another end portion having a third width that is a length extending in the second direction, and wherein the first width is less than each of the second width and the third width.

3. The semiconductor device according to claim 2 ,
wherein, in the plan view, the wire connecting portion of each of the plurality of second wires is located between the end portions.

4. A semiconductor device comprising:
a semiconductor chip having a first side, a second side opposite the first side, a first upper surface on which a plurality of electrodes is formed and a first back surface opposite the first upper surface;
a tab having a first side, a second upper surface to which the semiconductor chip is fixed;
a plurality of leads arranged along the first side of the tab in a plan view;
a plurality of first wires connecting a plurality of first electrodes of the plurality of electrodes with the plurality of leads, respectively;
a plurality of second wires connecting a plurality of second electrodes of the plurality of electrodes with the tab, respectively; and
a seal member sealing the semiconductor chip, the tab, a part of each of the plurality of leads, the plurality of first wires and the plurality of second wires,
wherein, in the plan view, the plurality of electrodes is arranged along the first side of the semiconductor chip,
wherein, in the plan view, the first side of the semiconductor chip extends in a first direction and is disposed between the second side of the semiconductor chip and the first side of the tab,
wherein, in the plan view, the first side of the tab extends along the first side of the semiconductor chip,
wherein, in the plan view, the first side of the tab is located between the first side of the semiconductor chip and the plurality of leads,
wherein, in the plan view, the tab has a slit that pierces the tab, and that is formed between the first side of the semiconductor chip and the first side of the tab,
wherein, in the plan view, the slit has a first portion extending in the first direction, a second portion and a third portion, each of the first portion, the second portion and the third portion having a width that is a length extending in a second direction crossing the first direction,
wherein the width of the first portion between the second and third portions is less than the width of each of the second and third portions,
wherein, in the plan view, a wire connecting portion of each of the plurality of second wires, which is connected to the tab, is located between the slit and the first side of the tab, and
wherein, in the plan view, each of the plurality of second wires intersects with the slit.

5. The semiconductor device according to claim 4 ,
wherein, in the plan view, the wire connecting portion of each of the plurality of second wires is located between the second and the third portions of the slit.

6. A semiconductor device comprising:
a semiconductor chip having a first side, a second side opposite the first side, a first upper surface on which a plurality of electrodes is formed and a first back surface opposite the first upper surface;
a tab having a first side, a second upper surface to which the semiconductor chip is fixed;
a plurality of leads arranged along the first side of the tab in a plan view;
a plurality of first wires connecting a plurality of first electrodes of the plurality of electrodes with the plurality of leads, respectively;
a plurality of second wires connecting a plurality of second electrodes of the plurality of electrodes with the tab, respectively; and
a seal member sealing the semiconductor chip, the tab, a part of each of the plurality of leads, the plurality of first wires and the plurality of second wires,
wherein, in the plan view, the plurality of electrodes is arranged along the first side of the semiconductor chip,
wherein, in the plan view, the first side of the semiconductor chip extends in a first direction and is disposed between the second side of the semiconductor chip and the first side of the tab,
wherein, in the plan view, the first side of the tab extends along the first side of the semiconductor chip,
wherein, in the plan view, the first side of the tab is located between the first side of the semiconductor chip and the plurality of leads,
wherein, in the plan view, the tab has a slit that pierces the tab, and that is formed between the first side of the semiconductor chip and the first side of the tab,
wherein, in the plan view, the slit has opposite sides and opposite end portions,
wherein a distance between the opposite sides at the opposite end portions of the slit is greater than a distance between the opposite sides at a central portion of the slit disposed between the opposite end portions,
wherein, in the plan view, a wire connecting portion of each of the plurality of second wires, which is connected to the tab, is located between the slit and the first side of the tab, and
wherein, in the plan view, each of the plurality of second wires intersects with the slit.

7. The semiconductor device according to claim 6 ,
wherein one of the opposite sides is a first side of the slit that extends along the first side of the semiconductor chip, and the opposite end portions of the slit extend from the central portion toward the first side of the tab in a second direction crossing the first direction.

Assignees

• Renesas Electronics Corp
• Renesas Semiconductor Package & Test Solutions Co Ltd

Inventors

• Hasebe Hajime
• Danno Tadatoshi
• Satou Yukihiro

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07353

  changes in shapes · CPC title