Semiconductor device

Patent metadata

Field	Value
Publication number	US-10115658-B2
Application number	US-201615293584-A
Country	US
Kind code	B2
Filing date	Oct 14, 2016
Priority date	Dec 28, 2000
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor chip having a first upper surface on which a plurality of electrodes are formed and a first back surface opposite the first upper surface;
a tab having a second upper surface to which the semiconductor chip is fixed;
a plurality of leads arranged along a first side of the tab in a plan view;
a plurality of first wires connecting a plurality of first electrodes of the plurality of electrodes with the plurality of leads, respectively;
a plurality of second wires connecting a plurality of second electrodes of the plurality of electrodes with the tab, respectively; and
a seal member sealing the semiconductor chip, the tab, a part of each of the plurality of leads, the plurality of first wires and the plurality of second wires,
wherein, in the plan view, the semiconductor chip has a second side along which the plurality of electrodes are arranged and extended in a first direction,
wherein, in the plan view, the first side of the tab is extended along the second side of the semiconductor chip,
wherein, in the plan view, the first side of the tab is located between the second side of the semiconductor chip and the plurality of leads,
wherein, in the plan view, the tab has a slit that pierces the tab formed between the second side of the semiconductor chip and the first side of the tab,
wherein, in the plan view, the slit has a first portion extended in the first direction, and a second portion extended from the first portion toward the first side of the tab and also extended in a second direction crossing the first direction,
wherein, in the plan view, a wire connecting portion of each of the plurality of second wires, which is connected to the tab, is located between the slit and the first side of the tab,
wherein, in the plan view, each of the plurality of second wires intersects with the slit, and
wherein a length of the first portion of the slit in the first direction is longer than a length of the second portion of the slit in the second direction.

2. The semiconductor device according to claim 1 ;
wherein, in the plan view, the second portion is formed in an end portion of the first portion, and
wherein, in the second direction, the wire connecting portion of each of the plurality of second wires is located between the first portion and the first side of the tab, but not located between the second portion and the first side of the tab.

3. The semiconductor device according to claim 1 ;
wherein the tab is obtained from a lead frame, and
wherein the plurality of leads is obtained from the lead frame.

4. The semiconductor device according to claim 1 ;
wherein, in the plan view, the seal member has a plurality of sides,
wherein, in the plan view, the seal member has a third side of the plurality of sides extended in the first direction,
wherein, in the plan view, the seal member has a fourth side of the plurality of sides extended in the second direction,
wherein, in the plan view, the third side of the seal member intersects with each of the plurality of leads,
wherein, in the plan view, the seal member has a slant face which is defined by the third side of the seal member and the fourth side of the seal member,
wherein the tab has a suspension lead extended from the tab toward the slant face of the seal member.

5. The semiconductor device according to claim 1 ;
wherein the tab has a second lower surface which is located opposite the second upper surface, and
wherein a part of the second lower surface is exposed from the seal member.

6. The semiconductor device according to claim 5 ,
wherein, in a cross-sectional view, a thickness of each of the plurality of leads is equal to a thickness of the tab.

7. The semiconductor device according to claim 1 ;
wherein the slit has a third portion extended from the first portion toward the first side of the tab and also extended in the second direction, and
wherein, in the second direction, the wire connecting portion of each of the plurality of second wires is located between the first portion and the first side of the tab, but not located between the second portion and the first side of the tab and between the third portion and the first side of the tab.

8. The semiconductor device according to claim 7 ;
wherein, in the plan view, the second portion is formed in an end portion of the first portion, and
wherein, in the plan view, the third portion is formed in other end portion of the first portion.

9. The semiconductor device according to claim 8 ;
wherein, in the plan view, the wire connecting portion of each of the plurality of second wires is located between the second portion and the third portion.

10. The semiconductor device according to claim 1 ;
wherein, in the plan view, one of the plurality of second wires is located between another of the plurality of second wires and the second portion in the first direction.

11. The semiconductor device according to claim 1 ;
wherein, each of the plurality of first wires intersects with the first side of the tab.

12. A semiconductor device comprising:
a semiconductor chip having a first upper surface on which a plurality of electrodes are formed and a first back surface opposite the first upper surface;
a tab having a second upper surface to which the semiconductor chip is fixed;
a plurality of leads arranged along a first side of the tab in a plan view;
a plurality of first wires connecting a plurality of first electrodes of the plurality of electrodes with the plurality of leads, respectively;
a plurality of second wires connecting a plurality of second electrodes of the plurality of electrodes with the tab, respectively; and
a seal member sealing the semiconductor chip, the tab, a part of each of the plurality of leads, the plurality of first wires and the plurality of second wires,
wherein, in the plan view, the semiconductor chip has a second side along which the plurality of electrodes are arranged and extended in a first direction,
wherein, in the plan view, the first side of the tab is extended along the second side of the semiconductor chip,
wherein, in the plan view, the first side of the tab is located between the second side of the semiconductor chip and the plurality of leads,
wherein, in the plan view, the tab has a slit that pierces the tab formed between the second side of the semiconductor chip and the first side of the tab,
wherein, in the plan view, the slit has a first portion extended in the first direction, and a second portion which is extended from the first portion toward the first side of the tab and also extended in a second direction crossing the first direction,
wherein, in the plan view, the first portion has a third side and a fourth side opposite the third side,
wherein, in the plan view, the fourth side of the first portion is extended along the second side of the semiconductor chip, and located between the third side of the first portion and the second side of the semiconductor chip,
wherein, in the plan view, the second portion has a fifth side extended in the second direction and opposite the fourth side of the first portion,
wherein, in the plan view, the fifth side of the second portion is located between the fourth side of the first portion and the first side of the tab,
wherein, a length from the second side of the semiconductor chip to the fifth side of the second portion is longer than a length from the second side of the semiconductor chip to the third side of the first portion,
wherein, in the plan view, a wire connecting portion of each of the plurality of second wires, which is connected to the tab,

Assignees

• Renesas Electronics Corp
• Renesas Semiconductor Package & Test Solutions Co Ltd

Inventors

• Hasebe Hajime
• Danno Tadatoshi
• Satou Yukihiro

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07353

  changes in shapes · CPC title