Method for blocking a trench portion

Patent metadata

Field	Value
Publication number	US-10490442-B2
Application number	US-201815903909-A
Country	US
Kind code	B2
Filing date	Feb 23, 2018
Priority date	Feb 23, 2017
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

An example embodiment may include a method for blocking one or more portions of one or more trenches during manufacture of a semiconductor structure. The method may include (i) providing a substrate comprising one or more trenches, and a dielectric material under the one or more trenches, (ii) providing a first overlayer on the substrate, thereby filling the one or more trenches, the first overlayer having a planar top surface, a top portion of the first overlayer, comprising the top surface, being etchable selectively with respect to a condensed photo-condensable metal oxide, (iii) covering a first area of the top surface, situated directly above the one or more portions and corresponding thereto, with a block pattern of the condensed photo-condensable metal oxide, thereby leaving a second area of the top surface, having at least another portion of at least one of the trenches thereunder, uncovered.

First claim

What is claimed is:

1. A method for blocking one or more portions of one or more trenches during manufacture of a semiconductor structure, the method comprising:
providing a substrate comprising one or more trenches, and a dielectric material under the one or more trenches,
providing a first overlayer on the substrate, thereby filling the one or more trenches, the first overlayer having a planar top surface, a top portion of the first overlayer, comprising the top surface, being etchable selectively with respect to a condensed photo-condensable metal oxide;
covering a first area of the top surface, situated directly above the one or more portions and corresponding thereto, with a block pattern of the condensed photo-condensable metal oxide, thereby leaving a second area of the top surface, having at least another portion of at least one of the trenches thereunder, uncovered;
covering the block pattern and the second area with a second overlayer having a planar top surface, a bottom portion of the second overlayer, in contact with the block pattern and the second area, being etchable selectively with respect to the condensed photo-condensable metal oxide and with respect to the top portion of the first overlayer;
providing a masking layer over the second overlayer, the masking layer having a via pattern; and
transferring the via pattern and the other portion of the at least one of the trenches into the dielectric material.

2. The method according to claim 1 , wherein, after covering the block pattern and the second area with a second overlayer, the second overlayer is directly in contact with the first overlayer.

3. The method according to claim 1 , wherein the first overlayer comprises a planarization layer filling completely the one or more trenches and, optionally, a hardmask layer thereon.

4. The method according to claim 3 , wherein the optional hardmask layer is a spin-on-glass, a SiO 2 , a SiOC or a Si 3 N 4 layer.

5. The method according to claim 1 , wherein, after providing the masking layer over the second overlayer, the second overlayer is directly in contact with the masking layer, with the block pattern and with the second area of the top surface.

6. The method according to claim 1 , wherein the second overlayer comprises a spin-on-glass layer and/or a spin-on-carbon layer.

7. The method according to claim 1 , wherein the second overlayer consists of a single material.

8. The method according to claim 1 , wherein the masking layer consists of a patterned photoresist layer on a hard mask layer or consists in a patterned condensed photo-condensable metal oxide layer.

9. The method according to claim 1 , wherein covering a first area of the top surface comprises:
providing a layer of a photo-condensable metal oxide;
exposing an area of the layer of photo-condensable metal oxide to a light source, such that the area of the layer condenses into the block pattern of condensed photo-condensable metal oxide; and
removing any uncondensed photo-condensable metal oxide.

10. The method according to claim 1 , wherein the one or more trenches comprise condensed photo-condensable metal oxide side walls.

11. The method according to claim 10 , wherein the one or more trenches comprise a bottom made of the dielectric material.

12. The method according to claim 1 , wherein one or more of the photo-condensable metal oxides comprise an organo-tin compound.

13. A semiconductor structure, comprising:
a substrate comprising one or more trenches, and a dielectric material under the one or more trenches;
a first overlayer on the substrate, filling the one or more trenches and having a planar top surface, a top portion of the first overlayer, comprising the top surface, being etchable selectively with respect to a condensed photo-condensable metal oxide;
a block pattern of a condensed photo-condensable metal oxide, the block pattern covering a first area of the top surface, the first area being situated directly above one or more portions of the one or more trenches and corresponding to these portions, a second area of the top surface, having at least another portion of at least one of the trenches thereunder, remaining uncovered; and
a second overlayer having a planar top surface, a bottom portion of the second overlayer, in contact with the block pattern and the second area, being etchable selectively with respect to the condensed photo-condensable metal oxide and with respect to the top portion of the first overlayer.

14. The structure according to claim 13 , further comprising:
a masking layer over the second overlayer, wherein the masking layer has a via pattern.

Assignees

• Imec Vzw

Inventors

• Chan Boon Teik
• Mao Ming
• De Schepper Peter
• Kocsis Michael

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title