Two-dimensional structure to form an embedded three-dimensional structure

US10490348B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10490348-B2
Application numberUS-201615192802-A
CountryUS
Kind codeB2
Filing dateJun 24, 2016
Priority dateJun 24, 2016
Publication dateNov 26, 2019
Grant dateNov 26, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus, comprising: a plurality of vias each having a defined shape, wherein each of the plurality of vias comprises: a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer; and a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects. 2. The apparatus of claim 1 , wherein the apparatus comprises an inductor device. 3. The apparatus of claim 2 , wherein the defined shape is a curved shape. 4. The apparatus of claim 3 , further comprising a magnetic core of the inductor device within an aperture defined by the curved shape of the plurality of vias. 5. The apparatus of claim 2 , wherein the defined shape is an “I” shape. 6. The apparatus of claim 1 , wherein the defined shape is a “C” shape. 7. The apparatus of claim 1 , wherein the defined shape is a semicircle shape. 8. The apparatus of claim 1 , wherein the apparatus comprises an embedded three-dimensional (3D) coil. 9. The apparatus of claim 1 , wherein the via directly couples the first two-dimensional conductive layer to the second two-dimensional conductive layer. 10. The apparatus of claim 1 , wherein the via substantially matches the defined shape. 11. The apparatus of claim 10 , wherein the defined shape is one of a “C” shape or a semicircle shape. 12. The apparatus of claim 1 , wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer are parallel to each other. 13. The apparatus of claim 12 , wherein a first portion of the first two-dimensional conductive layer is coplanar with a second portion of the second two-dimensional conductive layer. 14. The apparatus of claim 13 , wherein the first portion and the second portion are separated by the via. 15. An apparatus, comprising: a plurality of vias each having a defined shape, wherein each of the plurality of vias comprises: a first two-dimensional conductive means plated on a first side of a substrate, the first two-dimensional conductive means having the defined shape, a second two-dimensional conductive means plated on a second side of the substrate, the second two-dimensional conductive means having the defined shape, and means for conductively coupling the first two-dimensional conductive means to the second two-dimensional conductive means; and a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive means and the second two-dimensional conductive means of each of the plurality of vias are perpendicular to the plurality of interconnects. 16. The apparatus of claim 15 , wherein the apparatus comprises an inductor device. 17. The apparatus of claim 16 , wherein the defined shape is a curved shape. 18. The apparatus of claim 17 , further comprising a magnetic core of the inductor device within an aperture defined by the curved shape of the plurality of vias. 19. The apparatus of claim 16 , wherein the defined shape is an “I” shape. 20. The apparatus of claim 15 , wherein the defined shape is a “C” shape. 21. The apparatus of claim 15 , wherein the apparatus comprises an embedded three-dimensional (3D) coil.

Assignees

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Classifications

  • Package configurations · CPC title

  • the encapsulations exposing the passive side of the semiconductor body · CPC title

  • the substrate having spherical bumps for external connection · CPC title

  • Dispositions, e.g. layouts · CPC title

  • batch processes · CPC title

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What does patent US10490348B2 cover?
Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional condu…
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification H01F41/041. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 26 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).