Resistance change memory device

Patent metadata

Field	Value
Publication number	US-10490271-B2
Application number	US-201815915620-A
Country	US
Kind code	B2
Filing date	Mar 8, 2018
Priority date	Sep 20, 2017
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

According to one embodiment, a resistance change memory device comprises a memory cell array in which a plurality of resistance change storage elements each to store one of multiple resistance states as data represented in two or more bits are arranged, and a read unit to read the data of a selected one of the storage elements. In reading the data of the storage element, the read unit, selecting one at a time, applies multiple types of constant voltages to the storage element.

First claim

What is claimed is:

1. A resistance change memory device comprising:
a memory cell array in which a plurality of resistance change storage elements each to store one of multiple resistance states as data represented in two or more bits are arranged; and
a read unit to read the data of a selected one of the storage elements,
wherein in reading the data of the storage element, the read unit, selecting one at a time, applies multiple types of constant voltages to the storage element, and
wherein the read unit selects a constant voltage so as to read avoiding a forbidden region that is a set of phase transition points indicating operation points at which a phase transition occurs in the storage element.

2. The resistance change memory device according to claim 1 , wherein while sequentially selecting one of a plurality of reference voltages corresponding to a plurality of threshold resistances to determine which of the multiple resistance states the data of the storage element is, the read unit selects a next reference voltage and a next constant voltage to read, according to a result of comparing a first reference voltage that is a reference voltage selected first and a voltage when reading after applying a first constant voltage that is a constant voltage selected first to a bit line for supplying a voltage to the storage element.

3. The resistance change memory device according to claim 2 , wherein the first constant voltage selected first is a maximum voltage at which to be able to avoid the forbidden region, and an intersection of the maximum voltage and a maximum current at which to be able to avoid the forbidden region corresponds to a middle threshold resistance from among the plurality of threshold resistances.

4. The resistance change memory device according to claim 3 , wherein if the voltage on the bit line when reading after applying the first constant voltage exceeds the first reference voltage, the read unit selects a second reference voltage, higher than the first reference voltage, as a reference voltage corresponding to a threshold resistance higher by one step than the middle threshold resistance and selects a second constant voltage, higher than the first constant voltage, as a constant voltage so as to read, and
wherein setting is made such that operation points of the storage element when reading after applying the first constant voltage and the second constant voltage to the bit line avoid the forbidden region.

5. The resistance change memory device according to claim 4 , wherein if the voltage on the bit line when reading after applying a kth constant voltage (k≥3) exceeds a kth reference voltage, the read unit selects a k′th reference voltage, higher than the kth reference voltage, as a reference voltage corresponding to a threshold resistance higher by one step or more than the middle threshold resistance and selects a k′th constant voltage, higher than the kth constant voltage, as a constant voltage so as to read, and
wherein setting is made such that operation points of the storage element when reading after applying the kth and k′th constant voltages to the bit line avoid the forbidden region.

6. The resistance change memory device according to claim 4 , wherein after applying the first constant voltage and reading, on the way to reading after applying the second constant voltage, the read unit temporarily renders the storage element non-selected and then selects and, while the storage element is non-selected, precharges the bit line to the second constant voltage.

7. The resistance change memory device according to claim 3 , wherein if the voltage on the bit line when reading after applying the first constant voltage is smaller than the first reference voltage, the read unit selects a third reference voltage, smaller than the first reference voltage, as a reference voltage corresponding to a threshold resistance lower by one step than the middle threshold resistance and again selects the first constant voltage as a constant voltage so as to read, and
wherein setting is made such that operation points of the storage element when reading after applying the first constant voltage to the bit line avoid the forbidden region.

8. The resistance change memory device according to claim 7 , wherein if the voltage on the bit line when reading after applying the first constant voltage is smaller than the first reference voltage, the read unit selects a k″th reference voltage, smaller than the kth reference voltage, as a reference voltage corresponding to a threshold resistance higher by one step or more than the kth threshold resistance (k≥3) and again selects the first constant voltage as a constant voltage so as to read, and
wherein setting is made such that operation points of the storage element when reading after applying the kth constant voltage to the bit line avoid the forbidden region.

9. The resistance change memory device according to claim 7 , wherein after applying the first constant voltage and reading, on the way to reading after again applying the first constant voltage, the read unit temporarily renders the storage element non-selected and then selects and, while the storage element is non-selected, again precharges the bit line to the first constant voltage.

10. The resistance change memory device according to claim 4 , wherein if the voltage on the bit line when reading after applying the first constant voltage is smaller than the first reference voltage, the read unit selects a third reference voltage, lower than the first reference voltage, as a reference voltage corresponding to a threshold resistance lower by one step than the middle threshold resistance and does not again select the first constant voltage nor select another constant voltage, so as to perform a second read, and
wherein setting is made such that operation points of the storage element when reading after applying the first constant voltage to the bit line avoid the forbidden region.

11. A resistance change memory device comprising:
a memory cell array in which a plurality of resistance change storage elements each to store one of multiple resistance states as data represented in two or more bits are arranged; and
a read unit to read the data of a selected one of the storage elements,
wherein the read unit reads the data of the storage element while switching between a constant voltage read method which applies a constant voltage to read the data of the storage element and a constant current read method which applies a constant current to read the data of the storage element.

12. The resistance change memory device according to claim 11 , wherein the read unit switches from the constant voltage read method to the constant current read method to read the data of the storage element.

13. The resistance change memory device according to claim 12 , wherein the read unit first selects a first reference voltage corresponding to a middle threshold resistance of a plurality of threshold resistances to determine which of the multiple resistance states the data of the storage element is, and a first constant voltage, and
wherein if a voltage on a bit line, for supplying a voltage to the storage element, when reading after applying the first constant voltage exceeds the first reference voltage, the read unit selects a second reference voltage, higher than the first reference voltage, as a reference voltage corresponding to a threshold resistance higher by one step than the middle threshold resistance and applies, as a constant current, a maximum current that is a maximum current outside a forbidden region that is a set of phase transition points indicating operation p

Assignees

• Toshiba Memory Corp

Inventors

• Ogiwara Ryu
• Takashima Daisaburo

Classifications

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C11/5614

  using conductive bridging RAM [CBRAM] or programming metallization cells [PMC] · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title

• G11C2013/005

  Read using potential difference applied between cell electrodes · CPC title