Resistive memory device and operating method

Patent metadata

Field	Value
Publication number	US-9536605-B2
Application number	US-201514806780-A
Country	US
Kind code	B2
Filing date	Jul 23, 2015
Priority date	Oct 29, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

Provided are a resistive memory device including a plurality of memory cells, and a method of operating the resistive memory device. The resistive memory device includes a sensing circuit connected to a first signal line, to which a memory cell is connected, the sensing circuit sensing data stored in the memory cell based on a first reference current; and a reference time generator for generating a reference time signal that determines a time point when a result of the sensing is to be output, based on the first reference current.

First claim

What is claimed is:

1. A resistive memory device comprising:
a memory cell array including a memory cell connected to a first signal line and a second signal line;
a sensing circuit connected to the first signal line, wherein the sensing circuit is configured to sense data stored in the memory cell based on a first reference current flowing through the first signal line; and
a reference time generator is configured to generate a reference time signal that determines a time at which the sensing of the stored data by the sensing circuit occurs based on the first reference current,
wherein the sensing circuit comprises
a first current source configured to provide the first reference current to the first signal line,
a first capacitor connected to the first signal line, and
a sense amplifier configured to compare a first reference voltage with a voltage apparent on the first signal line in response to the reference time signal,

wherein the reference time generator comprises
a second current source configured to generate a second reference current based on the first reference current,
a second capacitor charged by the second reference current, and
a comparator configured to compare a second reference voltage with a voltage of the second capacitor and provide a corresponding comparison result as the reference time signal, and

wherein a time required for the first capacitor to be charged to a level of the first reference voltage in response to the first reference current is less than a time required for the second capacitor to be charged to a level of the second reference voltage in response to the second reference current.

2. The resistive memory device of claim 1 , wherein the second current source is configured to provide the second reference current that is a times greater than the first reference current, where 0<α<1.

3. The resistive memory device of claim 1 , wherein a capacitance of the first capacitor and a capacitance of the second capacitor are substantially equal.

4. The resistive memory device of claim 1 , wherein the first reference voltage and the second reference voltage are substantially equal.

5. The resistive memory device of claim 1 , wherein the second capacitor is a parasitic capacitor associated with the first signal line.

6. The resistive memory device of claim 1 , wherein the reference time generator is connected to a first dummy signal line of the memory cell array, and
the second capacitor is a parasitic capacitor associated with the first dummy signal line.

7. The resistive memory device of claim 1 , wherein the sensing circuit is configured to sense the data stored in the memory cell by executing a number of read operations, and
the reference time generator is configured to provide the sensing circuit with a plurality of reference time signals by changing a value of the second reference current in accordance with the number of read operations.

8. A resistive memory device comprising:
a memory cell array including a memory cell connected to a first signal line and a second signal line;
a sensing circuit configured to sense multi-level data stored in the memory cell based on a reference current and provide a sensing result in response to at least two reference time signals respectively activated at different times; and
a reference time generator including at least two reference time generation circuits configured to operate in response to the reference current and generate the at least two reference time signals, wherein each one of the at least two reference time generation circuits is configured to generate one of the at least two reference time signals,
wherein each one of the at least two reference time generation circuits is respectively configured to generate one of the at least two reference time signals based on at least two currents generated by reducing the reference current according to two different current reduction ratios.

9. The resistive memory device of claim 8 , wherein the sensing circuit comprises:
a first current source configured to provide the reference current to the first signal line;
a sense amplifier configured to compare a reference voltage with a voltage apparent on the first signal line to generate a first comparison result; and
at least two latches configured to receive the first comparison result and provide at least one bit of the multi-level data respectively in response to at least two reference time signals from among the at least two reference time signals.

10. The resistive memory device of claim 9 , wherein the at least two latches include a first latch, a second latch, and a third latch,
the first latch configured to provide a first bit of the multi-level data in response to a first reference time signal from the at least two reference time signals,
the second latch configured to provide a second bit data of the multi-level data in response to a second reference time signal from the at least two reference time signals, and
the third latch configured to provide a third bit of the multi-level data in response to a third reference time signal from the at least two reference time signals.

11. A method of operating a resistive memory device including a memory cell array including a memory cell connected to a first signal line and a second signal line, the method comprising:
providing a first reference current to the first signal line, wherein the first signal line is characterized by a first parasitic capacitor;
comparing a first reference voltage with a voltage apparent on the first signal line in response to a reference time signal to sense data stored in the memory cell, wherein the reference time signal is based on the first reference current;
generating a second reference current based on the first reference current;
charging a second parasitic capacitor associated with the second signal line using the second reference current; and
comparing a second reference voltage with a voltage of the second parasitic capacitor to provide a corresponding comparison result as the reference time signal,
wherein a time required for the first parasitic capacitor to be charged to a level of the first reference voltage in response to the first reference current is less than a time required for the second parasitic capacitor to be charged to a level of the second reference voltage in response to the second reference current.

12. The method of claim 11 , wherein a capacitance of the first parasitic capacitor and a capacitance of the second parasitic capacitor are substantially equal, and
the first reference voltage and the second reference voltage are substantially equal.

13. The method of claim 11 , wherein the second signal line is a dummy signal line of the memory cell array.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Hyun-Kook
• Lee Yeong-Taek
• Byeon Dae-Seok
• Kim Bo-Geun

Classifications

• G11C11/5685

  using storage elements comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title