Aggregation of interrupts using event queues

Patent metadata

Field	Value
Publication number	US-10489317-B2
Application number	US-201815960301-A
Country	US
Kind code	B2
Filing date	Apr 23, 2018
Priority date	Jun 10, 2014
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory configured to store data associated with a plurality of queues;
a plurality of root complexes, wherein each root complex of the plurality of root complexes is coupled to a respective plurality of endpoint devices and wherein a particular root complex is configured to:
receive a message from a requester device;
synthesize a virtual address using at least part of the message; and
an interface unit configured to store the message in a particular queue of the plurality of queues.

2. The apparatus of claim 1 , wherein the particular root complex is further configured to synthesize a request identification.

3. The apparatus of claim 2 wherein the particular root complex is further configured to translate the virtual address to a physical address.

4. The apparatus of claim 1 , wherein the message is associated with an Input/Output (I/O) interrupt associated with a particular endpoint device.

5. The apparatus of claim 1 , wherein the particular root complex is further configured determine a real address using the virtual address.

6. The apparatus of claim 1 , further comprising a processor configured to:
read, in response to executing one or more program instructions, event data previously stored in a second queue of the plurality of queues; and
select a particular execution thread of a plurality of execution threads executing on the processor using the event data.

7. A method, comprising:
receiving a request by a particular root complex of a plurality of root complexes coupled to respective pluralities of endpoint devices in a computing system;
synthesizing, by the particular root complex, a virtual address using at least part of the request; and
storing the request in an event data queue stored in a memory configured to store data associated with a plurality of queues.

8. The method of claim 7 , wherein the request includes a message signaled interrupt.

9. The method of claim 7 , wherein the request is associated with an Input/Output (I/O) interrupt associated with an endpoint device.

10. The method of claim 7 , further comprising translating the virtual address to a physical address.

11. The method of claim 10 , further comprising accessing a real translation cache memory to retrieve the physical address.

12. The method of claim 7 , further comprising synthesizing a requester identification using at least part of the request.

13. The method of claim 7 , further comprising selecting a particular execution thread of a plurality of execution threads executing on a particular processor core.

14. A system, comprising:
one or more memories, wherein at least one memory of the one or more memories is configured to store data associated with event data queue;
an endpoint device configured to send a message;
a plurality of root complexes, wherein a particular root complex is configured to:
receive the message;
synthesize a virtual address using at least part of the message; and
translate the virtual address to a physical address corresponding to a location in the one or more memories;

one or more processors; and
an interface unit configured to
store the message in a particular entry of event data queue.

15. The system of claim 14 , wherein the message includes a message signaled interrupt.

16. The system of claim 14 , wherein the message is associated with an Input/Output (I/O) interrupt associated with the endpoint device.

17. The system of claim 14 , wherein the particular root complex is further configured to synthesize a requester identification.

18. The system of claim 17 , wherein the requester identification includes a 16-bit peripheral component interface request identification.

19. The system of claim 14 , wherein the interface unit is further configured to store the message using the physical address.

20. The system of claim 14 , wherein a first processor of the one or more processors is configured to read, in response to executing one or more program instructions, event data previously stored in event data queue.

Assignees

• Oracle Int Corp

Inventors

• Feehrer John R
• Stabile Patrick
• Kurth Hugh R
• Kahn David M

Classifications

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F13/1605

  based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36) · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title