Aggregation of interrupts using event queues

Patent metadata

Field	Value
Publication number	US-9952989-B2
Application number	US-201615277146-A
Country	US
Kind code	B2
Filing date	Sep 27, 2016
Priority date	Jun 10, 2014
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory configured to store data associated with a plurality of queues;
a plurality of root complexes, wherein each root complex of the plurality of root complexes is coupled to a respective plurality of endpoint devices; and
an interface unit configured to:
receive a plurality of requests from the plurality of root complexes, wherein at least one request of the plurality of requests is made in response to an event associated with a particular endpoint device;
select a particular request of the plurality of requests using an arbitration algorithm; and
store information associated with the particular request in a first queue of the plurality of queues.

2. The apparatus of claim 1 , wherein the interface unit is further configured to select the first queue of the plurality of queues using a map.

3. The apparatus of claim 2 , wherein the particular request includes a request address, and wherein the interface unit is further configured to translate the request address to a physical address.

4. The apparatus of claim 1 , wherein the particular request is associated with an Input/Output (I/O) interrupt associated with the particular endpoint device.

5. The apparatus of claim 1 , wherein the arbitration algorithm includes a round robin scheduling algorithm.

6. The apparatus of claim 1 , further comprising a processor configured to:
read, in response to executing one or more program instructions, event data previously stored in a second entry of a second queue of the plurality of queues; and
select a particular execution thread of a plurality of execution threads executing on the processor using the event data and a first map.

7. A method, comprising:
receiving, from a plurality of root complexes in a computing system, a plurality of requests, wherein at least one request of the plurality of requests is made in response to an event associated with an endpoint device coupled to a particular root complex of the plurality of root complexes;
storing information associated with a particular request of the plurality of requests in a first entry of a first queue of a plurality of queues;
reading, by a software program executing on the computing system, data previously stored in a second entry of a second queue of the plurality of queues;
selecting a particular processor core of a plurality of processor cores included in the computing system using the data and a first map;
sending the data to the particular processor core; and
processing, by the particular processor core, a given event using the data.

8. The method of claim 7 , wherein the first map is programmable.

9. The method of claim 7 , wherein the particular request is associated with an Input/Output (I/O) interrupt associated with the endpoint device.

10. The method of claim 7 , wherein storing the information associated with the particular request includes retrieving pointer information associated with the first entry, and modifying the pointer information.

11. The method of claim 7 , further comprising selecting the particular request of the plurality of requests using an arbitration algorithm.

12. The method of claim 7 , wherein storing the information associated with the particular request includes selecting the first queue using a second map.

13. The method of claim 7 , wherein selecting the particular processor core includes selecting a particular execution thread of a plurality of execution threads executing on the particular processor core.

14. A system, comprising:
one or more memories, wherein at least one memory of the one or more memories is configured to store data associated with at least one queue of a plurality of queues;
a plurality of root complexes;
a plurality of processors; and
an interface unit configured to:
receive a plurality of requests from the plurality of root complexes, wherein at least one request of the plurality of requests is made in response to an event associated with an endpoint device coupled to a particular root complex of the plurality of root complexes;
store information associated with a particular request of the plurality of requests in a first entry of a first queue of the plurality of queues;

wherein a first processor of the plurality of processors is configured to:
read, in response to executing one or more program instructions, event data previously stored in a second entry of a second queue of the plurality of queues;
select a second processor of the plurality of processors using the event data and a first map;
send the event data to the second processor; and

wherein the second processor is configured to process a given event using the event data.

15. The system of claim 14 , wherein a particular processor of the plurality of processors is configured to modify, in response to executing at least one program instruction, the first map.

16. The system of claim 14 , wherein the particular request is associated with an Input/Output (I/O) interrupt associated with the endpoint device.

17. The system of claim 14 , wherein to store the information associated with the particular request, the interface unit is further configured to includes retrieving pointer information associated with the first entry, and modify the pointer information.

18. The system of claim 14 , wherein the interface unit is further configured to select the particular request of the plurality of requests using an arbitration algorithm.

19. The system of claim 14 , wherein to store the information associated with the particular request, the interface unit is further configured to select the first queue using a second map.

20. The system of claim 14 , wherein to select the second processor, the first processor is further configured to select a particular execution thread of a plurality of execution threads executing on the second processor.

Assignees

• Oracle Int Corp

Inventors

• Feehrer John R
• Stabile Patrick
• Kurth Hugh R
• Kahn David M

Classifications

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/1605

  based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36) · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title