Method for reducing interrupt latency in embedded systems

Patent metadata

Field	Value
Publication number	US-10489188-B2
Application number	US-201715825472-A
Country	US
Kind code	B2
Filing date	Nov 29, 2017
Priority date	Jan 19, 2017
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

The various embodiments of the present invention disclose a method for reducing interrupt latency in embedded systems. According to at least one example embodiment of the inventive concepts, the method for reducing interrupt latency in embedded systems, the method comprises steps of toggling, by a processor, from a supervisor (SVC) mode to an interrupt request (IRQ) mode on receiving an interrupt, identifying, by the processor, a Task Control Block (TCB) of a preempted task on receiving the interrupt, enabling, by the processor, the IRQ stack as a pseudo preempted task context table, and storing the preempted task context information in the IRQ stack, wherein a register set is stored in IRQ stack before processing the received interrupt.

First claim

What is claimed is:

1. A method for reducing interrupt latency in embedded systems, the method comprising:
toggling, by a processor, from a supervisor (SVC) mode to an interrupt request (IRQ) mode upon receiving an interrupt;
identifying, by the processor, a task control block (TCB) of a preempted task upon receiving the interrupt;
enabling, by the processor, an IRQ stack as a pseudo preempted task context table;
storing preempted task context information in the IRQ stack, wherein a register set is stored in the IRQ stack before processing the received interrupt; and
changing a stack pointer of the preempted task from pointing to a general stack to pointing to the stored preempted task context information in the IRQ stack, the general stack being a stack where the preempted task was executing prior to being preempted, the general stack being different from the IRQ stack.

2. The method of claim 1 , wherein the interrupt is received from at least one of an external entity, another processor, a direct memory access (DMA) engine, one or more co-processors, or one or more accelerators.

3. The method of claim 1 , wherein a configuration of the register set to be stored is one of static mode or dynamic mode.

4. The method of claim 1 , further comprising:
resetting the IRQ stack based on an occurrence of at least one of,
a real time operating system (RTOS) entering an IDLE mode; and
a context counter being set to zero.

5. The method of claim 4 , wherein the context counter is incremented with every context store operation on the IRQ stack, and the context counter is decremented with every context restore operation on the IRQ stack.

6. The method of claim 1 , wherein a stack size of the IRQ stack is defined when the IRQ stack is used as a pseudo preempted task context table, and the stack size of the IRQ stack is determined based on a number of priority tasks and a task context size.

7. The method of claim 1 , where the IRQ stack when used as a pseudo preempted task context table is stored in a fast access memory bank to speed up the store and restore operations.

8. The method of claim 1 , further comprising:
supporting an interrupt nesting when using the IRQ stack as a pseudo preempted task context table, where a nested interrupt context is also stored in the IRQ stack along with preempted task contexts and a nesting indicator global variable is set to identify interrupt nesting levels.

9. The method of claim 1 , further comprising:
identifying source of the received interrupt; and
starting an interrupt service routine.

10. An embedded device for reducing interrupts latency comprising:
a memory; and
a processor, coupled to the memory, configured to:
toggle from a supervisor (SVC) mode to an interrupt request (IRQ) mode on receiving an interrupt;
identify a task control block (TCB) of a preempted task based on receiving the interrupt;
enable an IRQ stack as a pseudo preempted task context table; and
store preempted task context information in the IRQ stack, wherein a register set is stored in the IRQ stack before processing the received interrupt;
wherein the processor is further configured to change a stack pointer of the preempted task from pointing to a general stack to pointing to the stored preempted task context information in the IRQ stack, the general stack being a stack where the preempted task was executing prior to being preempted, the general stack being different from the IRQ stack.

11. The embedded device of claim 10 , wherein the interrupt is received from at least one of an external entity, another processor, a direct memory access (DMA) engine, one or more co-processors, or one or more accelerators.

12. The embedded device of claim 10 , wherein a configuration of the register set to be stored is one of static mode or dynamic mode.

13. The embedded device of claim 10 , wherein the processor is further configured to:
reset the IRQ stack based on an occurrence of at least one of,
a real time operating system (RTOS) entering an IDLE mode; and
a context counter being set to zero.

14. The embedded device of claim 13 , wherein the context counter is incremented with every context store operation on the IRQ stack, and the context counter is decremented with every context restore operation on the IRQ stack.

15. The embedded device of claim 10 , wherein a stack size of the IRQ stack is defined when the IRQ stack is used as a pseudo preempted task context table, and the stack size of the IRQ stack is determined based on a number of priority tasks and a task context size.

16. The embedded device of claim 10 , wherein the IRQ stack when used as a pseudo preempted task context table is stored in a fast access memory bank to speed up the store and restore operations.

17. The embedded device of claim 10 , wherein the processor is further configured to:
support an interrupt nesting when using the IRQ stack as a pseudo preempted task context table, where a nested interrupt context is also stored in the IRQ stack along with preempted task contexts and a nesting indicator global variable is set to identify interrupt nesting levels.

18. The method of claim 1 , wherein the processor is further configured to:
identify source of the received interrupt; and
start a interrupt service routine.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Udava Raju Siddappa
• Somu Kandaswamy Balaji
• Reddy Patana Bhagwan
• Vrind Tushar
• Indukuri Venkata Raju

Classifications

• G06F9/461

  Saving or restoring of program or task context · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F9/4843

  by program, e.g. task dispatcher, supervisor, operating system · CPC title

• G06F9/463 Primary

  Program control block organisation · CPC title

• G06F9/462

  with multiple register sets · CPC title