Liquid Crystal Display Substrate and Preparation Method Thereof

Patent metadata

Field	Value
Publication number	US-2016274401-A1
Application number	US-201514744561-A
Country	US
Kind code	A1
Filing date	Jun 19, 2015
Priority date	Mar 17, 2015
Publication date	Sep 22, 2016
Grant date	—

Abstract

The present invention provides a liquid crystal display substrate and a preparation method thereof, which belongs to the technical field of liquid crystal display and may solve the problem that vias in the existing liquid crystal display substrate will result in non-uniform thickness of an alignment layer and thus influence the display effect. The liquid crystal display substrate provided by the present invention comprises a plurality of display structures, and an alignment layer located above all the display structures, wherein at least some of the display structures are provided therein with vias, and at least some of the vias are surrounded by baffle walls that are located under the alignment layer.

First claim

1 . A liquid crystal display substrate, comprising a plurality of display structures and an alignment layer is located above all the display structures, wherein at least some of the display structures are provided therein with vias, wherein,
at least some of the vias are surrounded by baffle walls.

2 . The liquid crystal display substrate according to claim 1 , wherein,
the alignment layer is formed by curing alignment liquid, and a height of the baffle wall is greater than or equal to a thickness of the alignment liquid for forming the alignment layer.

3 . The liquid crystal display substrate according to claim 1 , wherein,
the alignment layer is formed by curing alignment liquid, and a height of the baffle wall is less than or equal to a thickness of the alignment liquid for forming the alignment layer but greater than or equal to a thickness of the alignment layer.

4 . The liquid crystal display substrate according to claim 1 , wherein,
a width of the baffle wall ranges from 1000 nm to 100000 nm.

5 . The liquid crystal display substrate according to claim 1 , wherein a height of the baffle wall ranges from 50 nm to 3000 nm.

6 . The liquid crystal display substrate according to claim 1 , wherein,
the baffle wall is located above a topmost one of the display structures around the vias.

7 . The liquid crystal display substrate according to claim 1 , wherein,
the baffle wall is at least partially covered by the display structures around the vias.

8 . The liquid crystal display substrate according to claim 2 , wherein,
the baffle wall is at least partially covered by the display structures around the vias.

9 . The liquid crystal display substrate according to claim 3 , wherein,
the baffle wall is at least partially covered by the display structures around the vias.

10 . The liquid crystal display substrate according to claim 1 , wherein,
the baffle wall is composed of multiple layers of sub baffle walls.

11 . The liquid crystal display substrate according to claim 2 , wherein,
the baffle wall is composed of multiple layers of sub baffle walls.

12 . The liquid crystal display substrate according to claim 3 , wherein,
the baffle wall is composed of multiple layers of sub baffle walls.

13 . The liquid crystal display substrate according to claim 1 , wherein,
the baffle wall and at least one display structure are arranged in a same layer.

14 . The liquid crystal display substrate according to claim 1 , wherein,
the baffle wall is formed of conductive material.

15 . The liquid crystal display substrate according to claim 2 , wherein,
the baffle wall is formed of conductive material.

16 . The liquid crystal display substrate according to claim 3 , wherein,
the baffle wall is formed of conductive material.

17 . The liquid crystal display substrate according to claim 1 , wherein the liquid crystal display substrate is an array substrate;
each of the display structures comprises a drain of a thin film transistor, a passivation layer covering the drain, and a pixel electrode located on the passivation layer; and the vias comprise a via in the passivation layer, and the pixel electrode is connected to the drain of the thin film transistor through the via.

18 . A preparation method of the liquid crystal display substrate according to claim 1 , wherein the preparation method of the liquid crystal display substrate comprises the following steps:
forming a pattern comprising the baffle wall on a base substrate; and after preparing all the display structures, coating alignment liquid on the base substrate after the previous step, and curing the alignment liquid to form an alignment layer.

19 . The preparation method of a liquid crystal display substrate according to claim 18 , wherein the forming the pattern comprising the baffle wall on the base substrate comprises:
simultaneously forming a pattern comprising at least one display structure and the baffle wall on the base substrate.

20 . The preparation method of a liquid crystal display substrate according to claim 18 , wherein the forming the pattern comprising the baffle wall on the base substrate comprises:
separately forming a pattern of the baffle wall on the base substrate.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Huang Zhubing
• Jing Hui
• Wang Xiaofeng
• Ruan Defa
• Yu De

Classifications

• G02F1/133723 Primary

  Polyimide, polyamide-imide · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/13394 Primary

  spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence) · CPC title

• G02F1/136227 Primary

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F1/1337

  Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers · CPC title