Interposer substrate and method of fabricating the same

US10483194B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10483194-B2
Application numberUS-201815997849-A
CountryUS
Kind codeB2
Filing dateJun 5, 2018
Priority dateDec 3, 2014
Publication dateNov 19, 2019
Grant dateNov 19, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated.

First claim

Opening claim text (preview).

What is claimed is: 1. An interposer substrate, comprising: a second dielectric material layer having opposing first and second surfaces; a first wiring layer embedded in the second dielectric material layer and exposed from the first surface of the second dielectric material layer; a first dielectric material layer formed on the first surface of the second dielectric material layer and the first wiring layer, wherein a portion of the first wiring layer extends continuously into the first dielectric material layer from the second dielectric material layer, and the first dielectric material layer has a plurality of openings, from which a portion of the first wiring layer is exposed; a plurality of first conductive blocks embedded in the second dielectric material layer and having first terminal surfaces connected to the first wiring layer and second terminal surfaces opposing to the first terminal surfaces and flush with the second surface of the second dielectric material layer; a second wiring layer formed on the second surface of the second dielectric material layer and having a first side connected to the second terminal surfaces of the first conductive blocks and a second side opposing to the first surface of the second wiring layer; a plurality of second conductive blocks formed on the second side of the second wiring layer; and an insulative protection layer formed on the second surface of the second dielectric material layer, the second wiring layer and the second conductive blocks, wherein an end of the second conductive blocks is exposed from the insulative protection layer, and the insulative protection layer has at least a concave portion formed between two of the second conductive blocks. 2. The interposer substrate of claim 1 , further comprising a frame-type carrier formed on the first dielectric material layer. 3. The interposer substrate of claim 1 , wherein the portion of the first wiring layer exposed from the openings of the first dielectric material layer serves as bonding pads, for an external electronic component to be disposed on and electrically connected with the bonding pads via a plurality of conductive elements. 4. The interposer substrate of claim 1 , wherein the first wiring layer has a first portion embedded in the second dielectric material layer and a second portion formed in the openings of the first dielectric material layer. 5. The interposer substrate of claim 1 , wherein the first wiring layer having a surface flush with the first surface of the second dielectric material layer.

Assignees

Inventors

Classifications

  • Encapsulations, e.g. protective coatings · CPC title

  • on active surfaces of flip-chip devices, e.g. underfills · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • used as a support during the manufacture of self-supporting substrates · CPC title

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Frequently asked questions

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What does patent US10483194B2 cover?
The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second die…
Who is the assignee on this patent?
Phoenix Pioneer Technology Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W70/685. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 19 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).