Mechanisms for forming fine-pitch copper bump structures

Patent metadata

Field	Value
Publication number	US-9978656-B2
Application number	US-201213406270-A
Country	US
Kind code	B2
Filing date	Feb 27, 2012
Priority date	Nov 22, 2011
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

The mechanisms of forming a copper post structures described enable formation of copper post structures on a flat conductive surface. In addition, the copper post structures are supported by a molding layer with a Young's modulus (or a harder material) higher than polyimide. The copper post structures formed greatly reduce the risk of cracking of passivation layer and delamination of at the dielectric interface surrounding the copper post structures.

First claim

What is claimed is:

1. A semiconductor device structure on a semiconductor substrate, comprising:
a passivation layer over the semiconductor substrate;
an under-bump metallurgy (UBM) layer over the semiconductor substrate;
a first conductive structure over the UBM layer;
a copper post directly over the first conductive structure, wherein the copper post exposes a portion of a top surface of the first conductive structure;
a molding layer surrounding sidewalls of the copper post, wherein the molding layer covers the exposed portion of the top surface of the first conductive structure, and,
wherein a first portion of a top surface of the molding layer is curved, and a second portion of the top surface of the molding layer extends substantially parallel to a top surface of the semiconductor substrate; and
a second conductive structure over the semiconductor substrate, wherein the second portion of the molding layer covers an entire top surface of the second conductive structure, the passivation layer separates the second conductive structure from the semiconductor substrate, and a top surface of the first conductive structure is substantially coplanar with the top surface of the second conductive structure.

2. The semiconductor device structure of claim 1 , wherein the molding layer is made of thermosetting plastics.

3. The semiconductor device structure of claim 1 , wherein a width of the copper post is in a range from about 10 μm to about 105 μm.

4. The semiconductor device structure of claim 1 , wherein the semiconductor device structure comprises more than one copper posts and a pitch between the more than one copper posts is in a range from about 40 μm to about 180 μm.

5. The semiconductor device structure of claim 1 , wherein the first conductive structure is a top metal layer or a redistribution layer.

6. The semiconductor device structure of claim 1 , wherein a height of the molding layer surrounding the sidewalls of the copper post is in a range from about 5μm to about 60 μm above the structure conductive structure.

7. The semiconductor device structure of claim 1 , wherein the first conductive structure under the copper post has a width equal to or wider than a width of the copper post.

8. The semiconductor device structure of claim 1 , wherein a coefficient of thermal expansion of the molding layer is in a range from about 20 ppm/° C. to about 60 ppm/° C.

9. The semiconductor device structure of claim 1 , wherein the molding layer contacts with the passivation layer.

10. The semiconductor device structure of claim 1 , wherein the copper post lands completely on the first conductive structure.

11. The semiconductor device structure of claim 1 , wherein a thickness of the passivation layer is uniform across an entirety of the passivation layer.

12. The semiconductor device structure of claim 1 , wherein a second UBM layer is between the second conductive structure and the passivation layer, and the passivation layer directly contacts the semiconductor substrate.

13. A semiconductor device structure on a semiconductor substrate, comprising:
a contact pad over the semiconductor substrate;
a passivation layer extending over at least a portion of the contact pad, wherein an entirety of a top surface of the passivation layer is co-planar;
an under-bump metallurgy (UBM) layer over a portion of the passivation layer;
a conductive layer formed over the UBM layer;
a copper post formed directly over the conductive layer, wherein the copper post exposes a portion of a top surface of the conductive layer, and the copper post is positioned directly above the contact pad and centered with respect to the contact pad;
a second conductive layer separated from the conductive layer; and
a molding layer surrounding sidewalls of the copper post, the molding layer contacts the exposed portion of the top surface of the conductive layer, the molding layer directly contacts the passivation layer, a top surface of a first portion of the molding layer is substantially parallel to the top surface of the passivation layer, the first portion of the molding layer is over the second conductive layer, and a second portion of the molding layer between the first portion and the copper post has a curved top surface,
wherein the semiconductor device structure comprises more than one copper posts and a pitch of the more than one copper posts is in a range from about 40 μm to about 180 μm.

14. A method of forming a copper post structure on a substrate, comprising:
forming a passivation layer over the substrate
forming an UBM layer over the passivation layer, wherein the passivation layer has an opening exposing a conductive region;
forming a conductive layer over the UBM layer;
forming a copper post structure over the conductive layer, wherein forming the copper post structure comprises exposing a portion of a top surface of the conductive layer; and
forming a molding layer to surround the copper post structure, cover a top surface of the copper post structure, wherein forming the molding layer includes covering the exposed portion of the top surface of the conductive layer,
wherein a top surface of the molding layer has a discontinuous curve, a first portion of the top surface of the molding layer is curved, and a second portion of the top surface of the molding layer extends substantially parallel to a top surface of the substrate.

15. The method of claim 14 , wherein forming the molding layer comprises;
depositing a liquid molding compound on the substrate;
shaping the liquid molding compound by using an elastic film and by pressing the elastic film against the copper post structure; and
curing the liquid molding compound to form the molding layer.

16. The method of claim 15 , further comprising:
removing a thin molding layer from the top surface of the copper post structure.

17. The method of claim 14 , wherein the molding layer is made of thermosetting plastics.

18. The method of claim 14 , wherein the coefficient of thermal expansion of the molding layer is in a range from about 20 ppm/° C. to about 60 ppm/° C.

19. The method of claim 14 , wherein forming the molding layer comprises;
depositing a liquid molding compound on the substrate;
curing the liquid molding compound to form the molding layer; and
etching a portion of the molding layer to expose the copper post structure.

20. The method of claim 14 , wherein the copper post structure includes a copper post and a capping layer.

Assignees

• Lin Tsung Shu
• Pu Han Ping
• Cheng Ming Da
• Huang Chang Chia
• Liu Hao Juin
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Tsung-Shu
• Pu Han-Ping
• Cheng Ming-Da
• Huang Chang-Chia
• Liu Hao-Juin

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/921

  Structures or relative sizes of bond pads · CPC title