Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10482964-B2
Application number	US-201816040837-A
Country	US
Kind code	B2
Filing date	Jul 20, 2018
Priority date	Jan 8, 2016
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region. Each of the intermediate stack structures exposes the third stair step structure of the intermediate stack structure disposed thereunder.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device comprising:
a substrate comprising a cell array region and a connection region;
an electrode structure extending from the cell array region onto the connection region in a first direction, the electrode structure comprising a lower stack structure comprising a plurality of lower electrodes vertically stacked on the substrate and a plurality of intermediate stack structures vertically stacked on the lower stack structure to comprise a first stair step structure in the first direction;
an upper stack structure comprising a plurality of upper electrodes vertically stacked on the electrode structure; and
an upper dummy stack structure comprising a plurality of upper dummy electrodes which are horizontally spaced apart from the upper stack structure and are vertically stacked on the electrode structure,
wherein each of the plurality of intermediate stack structures comprises a plurality of intermediate electrodes vertically stacked to comprise a second stair step structure extending in a second direction that is substantially perpendicular to the first direction.

2. The 3D semiconductor memory device of claim 1 ,
wherein the plurality of intermediate electrodes of each of the plurality of intermediate stack structures comprise an uppermost one of the plurality of intermediate electrodes and remaining ones of the plurality of intermediate electrodes that are between the substrate and the uppermost one of the plurality of intermediate electrodes,
wherein the plurality of lower electrodes comprises an uppermost one of the plurality of lower electrodes and remaining ones of the plurality of lower electrodes that are between the substrate and the uppermost one of the plurality of lower electrodes,
wherein each of the remaining ones of the plurality of lower electrodes comprises a lower pad region exposed by one of the plurality of lower electrodes disposed immediately thereon on the connection region,
wherein each of the remaining ones of the plurality of intermediate electrodes comprises an intermediate pad region exposed by one of the plurality of intermediate electrodes disposed immediately thereon on the connection region,
wherein respective lengths of the intermediate pad regions in the first direction are substantially equal to each other,
wherein respective widths of the intermediate pad regions in the second direction are substantially equal to each other,
wherein the lower pad regions have respective lengths in the first direction and respective widths in the second direction,
wherein the lengths and the widths of the lower pad regions decrease as a vertical distance from the substrate increases, and
wherein the intermediate pad regions of the plurality of intermediate electrodes of each of the plurality of intermediate stack structures are arranged in the second direction in a plan view.

3. The 3D semiconductor memory device of claim 1 ,
wherein the plurality of upper electrodes comprises an uppermost one of the plurality of upper electrodes and remaining ones of the plurality of upper electrodes that are between the electrode structure and the uppermost one of the plurality of upper electrodes,
wherein each of the remaining ones of the plurality of upper electrodes comprises an upper pad region exposed by one of the plurality of upper electrodes disposed immediately thereon, and
wherein the upper pad regions are arranged in the first direction in a plan view.

4. The 3D semiconductor memory device of claim 3 ,
wherein the plurality of upper dummy electrodes comprise sidewalls that are substantially coplanar with a sidewall of an uppermost one of the plurality of intermediate stack structures on the connection region,
wherein the plurality of upper dummy electrodes have respective lengths in the first direction and respective widths in the second direction, and
wherein the lengths and the widths of the plurality of upper dummy electrodes decrease as a vertical distance from the substrate increases.

5. The 3D semiconductor memory device of claim 1 , wherein the upper stack structure comprises a third stair step structure extending in the first direction on the connection region.

6. The 3D semiconductor memory device of claim 1 , wherein the upper dummy stack structure comprises a fourth stair step structure extending in a direction opposite the first direction and a fifth stair step structure extending in the second direction.

7. A three-dimensional (3D) semiconductor memory device comprising:
a substrate comprising a cell array region and a connection region; and
an electrode structure extending from the cell array region onto the connection region in a first direction, the electrode structure comprising a plurality of stack structures vertically stacked on the substrate to comprise a first stair step structure extending in the first direction, each of the plurality of stack structures comprising a plurality of electrodes vertically stacked to comprise a second stair step structure extending in a second direction that is substantially perpendicular to the first direction,
wherein the substrate comprises a recessed portion adjacent to the electrode structure on the connection region.

8. The 3D semiconductor memory device of claim 7 , wherein the recessed portion comprises a bottom surface that is lower than a bottom surface of a lowermost one of the plurality of electrodes and comprises stepped sidewalls extending in the first and second directions, respectively.

9. The 3D semiconductor memory device of claim 8 , wherein the lowermost one of the plurality of electrodes includes an extended portion extending around the recessed portion of the substrate in a plan view.

10. The 3D semiconductor memory device of claim 7 , further comprising an upper stack structure comprising a plurality of upper electrodes vertically stacked on the electrode structure,
wherein the upper stack structure comprises a third stair step structure extending in the first direction and a fourth stair step structure extending in the second direction.

11. The 3D semiconductor memory device of claim 7 , wherein the recessed portion has a width in the second direction, and
wherein the width of the recessed portion decreases stepwise with a depth of the recessed portion.

12. The 3D semiconductor memory device of claim 7 , wherein, in each of the plurality of stack structures, sidewalls of the plurality of electrodes are substantially vertically aligned with each other.

13. The 3D semiconductor memory device of claim 7 , wherein a width of the recessed portion in the first direction decreases with a depth of the recessed portion.

14. The 3D semiconductor memory device of claim 7 , wherein each of the plurality of electrodes comprises:
a plurality of electrode portions extending in the first direction on the cell array region and spaced apart from each other in the second direction;
an electrode connection portion extending in the second direction on the connection region to horizontally connect the plurality of electrode portions to each other; and
a pad portion extending from the electrode connection portion in the first direction onto the connection region, the pad portion exposed by one of the plurality of electrodes, which is immediately thereon.

15. The 3D semiconductor memory device of claim 14 , wherein, in each of the plurality of stack structures, the pad portions of the plurality of electrodes are arranged along the second direction.

16. The 3D semiconductor memory device of claim 14 , further comprising contact plu

Assignees

• Jeong Da Woon
• Lee Sung Hun
• Yun Seokjung
• Park Hyunmog
• Shin Joongshik
• Yoon Young Bae
• Samsung Electronics Co Ltd

Inventors

• Jeong Da Woon
• Lee Sung-Hun
• Yun Seokjung
• Park Hyunmog
• Shin Joongshik
• Yoon Young-Bae

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title