Winograd algorithm on a matrix processing architecture

Patent metadata

Field	Value
Publication number	US-10482155-B2
Application number	US-201615395542-A
Country	US
Kind code	B2
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

In one embodiment, a matrix operation may be performed, wherein the matrix operation comprises a matrix multiplication operation on a plurality of matrix operands. Matrix data may be received from a multi-dimensional memory, wherein the matrix data is associated with the plurality of matrix operands. The plurality of matrix operands may be extracted from the matrix data, wherein the plurality of matrix operands comprises a first matrix operand and a second matrix operand. A first transform may be performed on the first matrix operand to obtain a transformed matrix operand, wherein performing matrix multiplication using the transformed matrix operand is faster than performing matrix multiplication using the first matrix operand. Matrix multiplication may be performed on the transformed matrix operand to obtain a partial result. A second transform may be performed on the partial result to obtain a result of the matrix multiplication operation.

First claim

What is claimed is:

1. A matrix processing circuit, comprising:
a plurality of memory resource blocks (MRBs);
a plurality of matrix processing units (MPUs) comprising circuitry to perform a plurality of matrix multiplication operations; and
circuitry to:
load matrix data associated with the plurality of matrix multiplication operations into a first subset of the plurality of MRBs, wherein the matrix data comprises image data and interleaved convolution filter data, wherein the interleaved convolution filter data comprises a plurality of convolution filter matrices that are interleaved with each other;
extract a plurality of matrix operands from the matrix data in the first subset of the plurality of MRBs, wherein the plurality of matrix operands are extracted into a second subset of the plurality of MRBs, and wherein the plurality of matrix operands comprise an image matrix and the plurality of convolution filter matrices, wherein the image matrix is extracted from the image data and the plurality of convolution filter matrices are extracted from the interleaved convolution filter data;
perform a first transform on the image matrix to obtain a transformed image matrix, wherein matrix multiplication of the transformed image matrix with each of the plurality of convolution filter matrices comprises fewer multiplication computations than matrix multiplication of the image matrix with each of the plurality of convolution filter matrices;
cause the plurality of matrix multiplication operations to be performed by the plurality of MPUs, wherein the plurality of matrix multiplication operations comprise multiplying the transformed image matrix with each of the plurality of convolution filter matrices to produce a plurality of transformed matrix multiplication results; and
perform a second transform on the plurality of transformed matrix multiplication results to obtain a plurality of final matrix multiplication results.

2. The matrix processing circuit of claim 1 , wherein the first transform is a Winograd input transform.

3. The matrix processing circuit of claim 1 , wherein the second transform is a Winograd output transform.

4. The matrix processing circuit of claim 1 , further comprising a transform routine memory, wherein the transform routine memory comprises one or more transform routines associated with one or more transform operations.

5. The matrix processing circuit of claim 4 , further comprising circuitry to:
receive a first transform routine from the transform routine memory, wherein the first transform routine is associated with the first transform; and
perform the first transform by executing the first transform routine.

6. The matrix processing circuit of claim 4 , further comprising circuitry to:
receive a second transform routine from the transform routine memory, wherein the second transform routine is associated with the second transform; and
perform the second transform by executing the second transform routine.

7. The matrix processing circuit of claim 1 , wherein the plurality of convolution filter matrices are for a plurality of convolution operations on the image data.

8. The matrix processing circuit of claim 1 , wherein the circuitry to extract the plurality of matrix operands from the matrix data in the first subset of the plurality of MRBs is further to slice the matrix data to extract the plurality of matrix operands.

9. The matrix processing circuit of claim 1 , wherein the plurality of matrix multiplication operations are associated with a forward propagation operation in a neural network.

10. The matrix processing circuit of claim 1 , wherein the plurality of matrix multiplication operations are associated with a backward propagation operation in a neural network.

11. A method, comprising:
receiving, by a matrix processing circuit, matrix data associated with a plurality of matrix multiplication operations, wherein:
the matrix processing circuit comprises a plurality of memory resource blocks (MRBs) and a plurality of matrix processing units (MPUs), wherein the plurality of MPUs comprise circuitry to perform matrix multiplication; and
the matrix data comprises image data and interleaved convolution filter data, wherein the interleaved convolution filter data comprises a plurality of convolution filter matrices that are interleaved with each other;

loading, by the matrix processing circuit, the matrix data into a first subset of the plurality of MRBs;
extracting, by the matrix processing circuit, a plurality of matrix operands from the matrix data in the first subset of the plurality of MRBs, wherein the plurality of matrix operands are extracted into a second subset of the plurality of MRBs, and wherein the plurality of matrix operands comprise an image matrix and the plurality of convolution filter matrices, wherein the image matrix is extracted from the image data and the plurality of convolution filter matrices are extracted from the interleaved convolution filter data;
performing, by the matrix processing circuit, a first transform on the image matrix to obtain a transformed image matrix, wherein matrix multiplication of the transformed image matrix with each of the plurality of convolution filter matrices comprises fewer multiplication computations than matrix multiplication of the image matrix with each of the plurality of convolution filter matrices;
causing, by the matrix processing circuit, the plurality of matrix multiplication operations to be performed by the plurality of MPUs, wherein the plurality of matrix multiplication operations comprise multiplying the transformed image matrix with each of the plurality of convolution filter matrices to produce a plurality of transformed matrix multiplication results; and
performing, by the matrix processing circuit, a second transform on the plurality of transformed matrix multiplication results to obtain a plurality of final matrix multiplication results.

12. The method of claim 11 , wherein:
the first transform is a Winograd input transform; and
the second transform is a Winograd output transform.

13. The method of claim 11 , further comprising:
receiving a first transform routine from a transform routine memory, wherein the first transform routine is associated with the first transform;
performing the first transform by executing the first transform routine;
receiving a second transform routine from the transform routine memory, wherein the second transform routine is associated with the second transform; and
performing the second transform by executing the second transform routine.

14. The method of claim 11 , wherein the plurality of convolution filter matrices are for a plurality of convolution operations on the image data.

15. A system, comprising:
a processor to execute a plurality of instructions associated with an application, wherein one or more of the plurality of instructions are associated with a plurality of matrix multiplication operations; and
matrix processing circuitry to perform the plurality of matrix multiplication operations, wherein the matrix processing circuitry comprises:
a plurality of memory resource blocks (MRBs);
a plurality of matrix processing units (MPUs) comprising circuitry to perform matrix multiplication; and
circuitry to:
load matrix data associated with the plurality of matrix multiplication operations into a first subset of the plurality of MRBs, wherein the matrix data comprises image data and interleaved convolution filter data, wherein the interleaved convolution filter data comprises a plurality of convolution filter matrices that are interleaved with each o

Assignees

• Intel Corp

Inventors

• Werner Tony L
• Kalaiah Aravind

Classifications

• G06F17/153

  Multidimensional correlation or convolution · CPC title

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F17/144

  Prime factor Fourier transforms, e.g. Winograd transforms, number theoretic transforms · CPC title