Dimension shuffling using matrix processors

Patent metadata

Field	Value
Publication number	US-2018189227-A1
Application number	US-201615395906-A
Country	US
Kind code	A1
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Jul 5, 2018
Grant date	—

Abstract

In one embodiment, a matrix operation may be performed to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory. Data associated with the input matrix may be accessed using one or more strided memory operations, wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval. The data accessed using the one or more strided memory operations may be stored in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.

First claim

What is claimed is:

1 . An apparatus, comprising:
a memory element comprising two-dimensional memory; and a processor to perform a matrix operation to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory, wherein the processor is configured to:
access data associated with the input matrix using one or more strided memory operations, wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval; and
store the data accessed using the one or more strided memory operations in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.

2 . The apparatus of claim 1 , wherein the matrix operation comprises a dimension shuffle operation to reorder the plurality of dimensions of the input matrix.

3 . The apparatus of claim 1 , wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of rows that are separated by the particular interval, wherein the particular interval comprises a particular number of rows.

4 . The apparatus of claim 1 , wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of columns that are separated by the particular interval, wherein the particular interval comprises a particular number of columns.

5 . The apparatus of claim 1 :
wherein the one or more strided memory operations are each configured to begin accessing the two-dimensional memory at a particular offset; and wherein the processor is further configured to store the data in the result matrix based on an order in which the data is accessed using the one or more strided memory operations.

6 . The apparatus of claim 1 , wherein the one or more strided memory operations comprise one or more convolutional read operations, the one or more convolutional read operations comprising at least one of:
a non-transpose convolutional read, wherein data accessed using the non-transpose convolutional read is stored in the result matrix in non-transpose form; or a transpose convolutional read, wherein data accessed using the transpose convolutional read is stored in the result matrix in transpose form.

7 . The apparatus of claim 6 , wherein the one or more convolutional read operations comprise at least one non-transpose convolutional read and at least one transpose convolutional read.

8 . The apparatus of claim 6 :
wherein the non-transpose form comprises a same form in which the data is accessed in the two-dimensional memory; and wherein the transpose form comprises a form in which the data accessed in the two-dimensional memory is transposed.

9 . The apparatus of claim 1 , wherein the matrix operation is associated with a convolution operation in a neural network.

10 . The apparatus of claim 1 , wherein the matrix operation is associated with a backward propagation operation in a neural network.

11 . A method, comprising:
performing a matrix operation to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory, wherein performing the matrix operation comprises:
accessing data associated with the input matrix using one or more strided memory operations, wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval; and
storing the data accessed using the one or more strided memory operations in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.

12 . The method of claim 11 , wherein the matrix operation comprises a dimension shuffle operation to reorder the plurality of dimensions of the input matrix.

13 . The method of claim 11 , wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of rows that are separated by the particular interval, wherein the particular interval comprises a particular number of rows.

14 . The method of claim 11 , wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of columns that are separated by the particular interval, wherein the particular interval comprises a particular number of columns.

15 . The method of claim 11 :
wherein the one or more strided memory operations each begin accessing the two-dimensional memory at a particular offset; and wherein the data is stored in the result matrix based on an order in which the data is accessed using the one or more strided memory operations.

16 . The method of claim 11 , wherein the one or more strided memory operations comprise a plurality of convolutional read operations, the plurality of convolutional read operations comprising:
a non-transpose convolutional read, wherein data accessed using the non-transpose convolutional read is stored in the result matrix in non-transpose form; and a transpose convolutional read, wherein data accessed using the transpose convolutional read is stored in the result matrix in transpose form.

17 . A system, comprising:
a memory element comprising two-dimensional memory; a plurality of processing elements, comprising:
a host processor;
one or more matrix processing chips;
a plurality of matrix processors associated with the one or more matrix processing chips;
wherein a matrix processor of the plurality of matrix processors is to perform a matrix operation to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory, wherein the matrix processor is configured to:
access data associated with the input matrix using one or more strided memory operations, wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval; and
store the data accessed using the one or more strided memory operations in a result matrix, wherein the data accessed using each strided memory operation is stored in the result matrix in non-transpose form or transpose form.

18 . The system of claim 17 , wherein the one or more strided memory operations comprise a plurality of convolutional read operations, the plurality of convolutional read operations comprising:
a non-transpose convolutional read, wherein data accessed using the non-transpose convolutional read is to be stored in the result matrix in non-transpose form; and a transpose convolutional read, wherein data accessed using the transpose convolutional read is to be stored in the result matrix in transpose form.

19 . At least one machine accessible storage medium having instructions stored thereon, the instructions, when executed on a machine, cause the machine to:
perform a matrix operation to reorder a plurality of dimensions of an input matrix stored in two-dimensional memory, wherein the instructions that cause the machine to perform the matrix operation further cause the machine to:
access data associated with the input matrix using one or more strided memory operations, wherein the one or more strided memory operations are configured to access the two-dimensional memory at a plurality of locations that are separated by a particular interval; and
store the data accessed using the one or more strided memory operations in

Assignees

• Intel Corp

Inventors

• Korthikanti Vijay Anand R
• Kalaiah Aravind
• Werner Tony L
• Khosrowshahi Amir

Classifications

• G06F9/30032 Primary

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F15/17343 Primary

  wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture (reconfigurable processors arrays G06F15/7867) · CPC title

• G11C5/05

  Supporting of cores in matrix · CPC title

• G06N3/0436

  Physics · mapped topic

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title