Link role determination in a dual-mode Peripheral Component Interconnect express (PCIe) device

Patent metadata

Field	Value
Publication number	US-10482050-B2
Application number	US-201715722783-A
Country	US
Kind code	B2
Filing date	Oct 2, 2017
Priority date	Nov 9, 2016
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

Link role determination in a dual-mode Peripheral Component Interconnect express (PCIe) device is disclosed. In this regard, determining a link role for a dual-mode PCIe device involves configuring the dual-mode PCIe device to operate in a root complex (RC) mode or an endpoint mode. The dual-mode PCIe device first performs a configuration and initiation sequence on a wire-based PCIe link in the RC mode. If the configuration and initiation sequence on the wire-based PCIe link is unsuccessful, then the dual-mode PCIe device invokes a random delay and switches to the endpoint mode at expiration of the random delay. By determining a link role of the dual-mode PCIe device based on the configuration and initiation sequence, it is possible to configure dynamically the dual-mode PCIe device to operate in the RC mode or the endpoint mode, thus allowing flexible configuration of the dual-mode PCIe device based on various application scenarios.

First claim

What is claimed is:

1. A dual-mode Peripheral Component Interconnect express (PCIe) device configured to operate in a root complex (RC) mode or an endpoint mode, comprising:
a bus interface configured to be coupled to a wire-based PCIe link; and
control circuitry configured to:
initialize the dual-mode PCIe device into the RC mode;
perform a configuration and initiation sequence on the wire-based PCIe link via the bus interface;
determine a link state of the wire-based PCIe link upon completion of the configuration and initiation sequence;
use a random delay when the link state indicates that the configuration and initiation sequence performed on the wire-based PCIe link is unsuccessful; and
switch the dual-mode PCIe device to the endpoint mode at expiration of the random delay.

2. The dual-mode PCIe device of claim 1 , wherein the control circuitry is further configured to configure the dual-mode PCIe device to operate in the RC mode when the link state indicates that the configuration and initiation sequence performed on the wire-based PCIe link is successful.

3. The dual-mode PCIe device of claim 1 , wherein the control circuitry is further configured to:
determine the link state of the wire-based PCIe link after switching the dual-mode PCIe device to the endpoint mode at the expiration of the random delay;
use the random delay when the link state indicates that the configuration and initiation sequence performed on the wire-based PCIe link is unsuccessful; and
switch the dual-mode PCIe device to the RC mode at the expiration of the random delay.

4. The dual-mode PCIe device of claim 3 , wherein the control circuitry is further configured to configure the dual-mode PCIe device to operate in the endpoint mode when the link state indicates that the configuration and initiation sequence performed on the wire-based PCIe link is successful.

5. The dual-mode PCIe device of claim 1 , wherein the control circuitry is configured to use the random delay after a delay of one millisecond from determining that the configuration and initiation sequence performed on the wire-based PCIe link is unsuccessful.

6. The dual-mode PCIe device of claim 1 , wherein the control circuitry is configured to use the random delay corresponding to a temporal delay between fifty and one hundred milliseconds.

7. The dual-mode PCIe device of claim 1 , wherein the control circuitry is further configured to enable a Link Training and Status state machine (LTSSM) prior to performing the configuration and initiation sequence on the wire-based PCIe link.

8. The dual-mode PCIe device of claim 7 , wherein the control circuitry is further configured to disable the LTSSM prior to initializing the dual-mode PCIe device into the endpoint mode.

9. The dual-mode PCIe device of claim 1 integrated into an integrated circuit (IC).

10. The dual-mode PCIe device of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.); a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

11. A method for configuring a dual-mode Peripheral Component Interconnect express (PCIe) device to operate in a root complex (RC) mode or an endpoint mode, comprising:
initializing the dual-mode PCIe device into the RC mode;
performing a configuration and initiation sequence on a wire-based PCIe link coupled to the dual-mode PCIe device;
determining a link state of the wire-based PCIe link upon completion of the configuration and initiation sequence;
using a random delay when the link state indicates that the configuration and initiation sequence performed on the wire-based PCIe link is unsuccessful; and
switching the dual-mode PCIe device to the endpoint mode at expiration of the random delay.

12. The method of claim 11 , further comprising configuring the dual-mode PCIe device to operate in the RC mode when the link state indicates that the configuration and initiation sequence performed on the wire-based PCIe link is successful.

13. The method of claim 11 , further comprising:
determining the link state of the wire-based PCIe link after switching the dual-mode PCIe device to the endpoint mode at the expiration of the random delay;
using the random delay when the link state indicates that the configuration and initiation sequence performed on the wire-based PCIe link is unsuccessful; and
switching the dual-mode PCIe device to the RC mode at the expiration of the random delay.

14. The method of claim 13 , further comprising configuring the dual-mode PCIe device to operate in the endpoint mode when the link state indicates that the configuration and initiation sequence performed on the wire-based PCIe link is successful.

15. The method of claim 11 , further comprising using the random delay after a delay of one millisecond from determining that the configuration and initiation sequence performed on the wire-based PCIe link is unsuccessful.

16. The method of claim 11 , further comprising using the random delay corresponding to a temporal delay between fifty and one hundred milliseconds.

17. The method of claim 11 , further comprising enabling a Link Training and Status state machine (LTSSM) prior to performing the configuration and initiation sequence on the wire-based PCIe link.

18. The method of claim 17 , further comprising disabling the LTSSM prior to initializing the dual-mode PCIe device into the endpoint mode.

19. A Peripheral Component Interconnect express (PCIe) system, comprising:
a dual-mode PCIe device configured to operate in a root complex (RC) mode or an endpoint mode, comprising:
a bus interface configured to be coupled to a wire-based PCIe link; and
control circuitry configured to:
initialize the dual-mode PCIe device into the RC mode;
perform a configuration and initiation sequence on the wire-based PCIe link via the bus interface;
determine a link state of the wire-based PCIe link upon completion of the configuration and initiation sequence;
use a random delay when the link state indicates that the configuration and initiation sequence performed on the wire-based PCIe link is unsuccessful; and
switch the dual-mode PCIe device to the endpoint mode at expiration of the random delay; and

a second dual-mode PCIe device configured to operate in the RC mode or the endpoint mode, comprising:
a second bus interface configured to be coupled to the wire-based PCIe link; and
second control circuitry configured to:
initialize the second dual-mode PCIe device into the RC mode;
perform a second configuration and initiation sequence on the wire-based PCIe link via the second bus interface;
determine a second link state of the wire-based PCIe link upon completion of the second configuration and initiation sequence;
use a second random delay when the second link state indi

Assignees

• Qualcomm Inc

Inventors

• Klacar Neven
• He Yan
• Krishna Murali

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/385 Primary

  for adaptation of a particular data processing system to different peripheral devices · CPC title