Hard switching disable for switching power device

Patent metadata

Field	Value
Publication number	US-10477626-B2
Application number	US-201715464130-A
Country	US
Kind code	B2
Filing date	Mar 20, 2017
Priority date	Nov 23, 2016
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A controller for driving a power switch incorporates a hard turn-on disable circuit to prevent the power switch from turning on when the power switch is sustaining a high voltage value. The hard turn-on disable circuit includes a hard turn-on detection circuit and a protection logic circuit. The hard turn-on disable circuit is configured to block or to pass the system input signal to the normal gate drive circuit of the power switch depending on the detection indicator signal. In particular, the protection logic circuit blocks the system input signal V IN in response to a high voltage detection so that the power switch ignores the system input signal V IN , which may be erroneous, and the power switch is prevented from undesirable hard switching.

First claim

What is claimed is:

1. A controller circuit for generating a gate drive signal on an output node for driving a gate terminal of a power switch where the gate terminal controls the current flow between first and second power terminals of the power switch, the controller circuit comprising:
a first gate drive circuit configured to receive an input control signal and to generate a first output signal as the gate drive signal to drive the gate terminal of the power switch to turn on and off the power switch responsive to the input control signal, the first output signal having a first gate voltage value to drive the gate terminal of the power switch to turn on the power switch; and
a hard turn-on disable circuit configured to generate the input control signal in response to a system input signal and a first voltage indicative of a voltage across the first and second power terminals of the power switch, the system input signal determining an on-period and off-period of the power switch, the hard turn-on disable circuit generating a high voltage indicator signal, the high voltage indicator signal being asserted in response to the first voltage exceeding a first threshold level and being deasserted otherwise,
wherein while the power switch is in an off state in response to the system input signal and in response to the high voltage indicator signal being asserted, the hard turn-on disable circuit generates the input control signal having a first logical state to block the system input signal from being provided to the first gate drive circuit, and in response to the high voltage indicator signal being deasserted, the hard turn-on disable circuit generates the input control signal mirroring the system input signal to drive the first gate drive circuit.

2. The controller circuit of claim 1 , wherein the hard turn-on disable circuit comprises a hysteresis detection circuit having a set voltage level and a reset voltage level, the set voltage level being higher than the reset voltage level, the hysteresis detection circuit asserting the high voltage indicator signal in response to the first voltage being at or above the set voltage level and deasserting the high voltage indicator signal in response to the first voltage being at or below the reset voltage level.

3. The controller circuit of claim 2 , wherein the hard turn-on disable circuit further comprises a D-flip-flop having a data input terminal coupled to a positive power supply voltage, a clock input terminal coupled to the system input signal, a reset terminal coupled to a signal indicative of the high voltage indicator signal and generating an output signal, wherein the D-flip-flop is put in a reset mode in response to the high voltage indicator signal being asserted.

4. The controller circuit of claim 3 , wherein the hard turn-on disable circuit further comprises a logical AND gate configured to receive the system input signal and the output signal of the D-flip-flop, the logical AND gate generating the input control signal.

5. The controller circuit of claim 1 , wherein:
the first gate drive circuit comprises a first transistor, a first impedance, a second impedance and a second transistor connected in series between a positive power supply voltage and a ground voltage, a common node between the first impedance and the second impedance being the output node,
wherein the first gate drive circuit turns on the first transistor and turns off the second transistor to assert the first output signal to turn on the power switch and the first gate drive circuit turns off the first transistor and turns on the second transistor to deassert the first output signal to turn off the power switch; and
wherein in response to the high voltage indicator signal being asserted, the first gate drive circuit turns off the first transistor and turns on the second transistor to deassert the first output signal to turn off the power switch.

6. The controller circuit of claim 1 , wherein the first voltage is indicative of a voltage across the first and second power terminals of the power switch during the off-period of the power switch.

7. The controller circuit of claim 1 , wherein the power switch comprises an insulated gate bipolar transistor (IGBT) device.

8. A method of generating a gate drive signal for driving a gate terminal of a power switch where the gate terminal controls the current flow between first and second power terminals of the power switch, the method comprising:
monitoring a feedback voltage indicative of a voltage across the first and second power terminals of the power switch;
providing a high voltage indicator signal;
determining the feedback voltage exceeding a first threshold level during the off-period of the power switch;
in response to the determining the feedback voltage exceeding the first threshold level, asserting the high voltage indicator signal;
determining the feedback voltage being below the first threshold level during the off-period of the power switch;
in response to the determining the feedback voltage being below the first threshold level, deasserting the high voltage indicator signal;
in response to the high voltage indicator signal being deasserted during the off-period of the power switch, providing a system input signal to drive the power switch to turn on and off, the system input signal determining an on-period and off-period of the power switch; and
in response to the high voltage indicator signal being asserted during the off-period of the power switch, blocking the system input signal from the power switch, the power switch being turned off regardless of the states of the system input signal.

9. The method of claim 8 , wherein determining the feedback voltage exceeding the first threshold level comprises determining the feedback voltage exceeding a set voltage level; and determining the feedback voltage being below the first threshold level comprises determining the feedback voltage being below a reset voltage level, the set voltage level being higher than the reset voltage level.

10. The method of claim 9 , further comprising:
subsequent to asserting the high voltage indicator signal, deasserting the high voltage indicator signal in response to the feedback voltage decreasing below the reset voltage level.

11. The method of claim 8 , wherein monitoring a feedback voltage indicative of a voltage across the first and second power terminals of the power switch comprises monitoring a feedback voltage indicative of a voltage across the first and second power terminals of the power switch during the off-period of the power switch.

12. A controller circuit for generating a gate drive signal on an output node for driving a gate terminal of a power switch where the gate terminal controls the current flow between first and second power terminals of the power switch, the controller circuit comprising:
a first gate drive circuit configured to receive an input control signal and to generate a first output signal as the gate drive signal to drive the gate terminal of the power switch to turn on and off the power switch responsive to the input control signal, the first output signal having a first gate voltage value to drive the gate terminal of the power switch to turn on the power switch;
a first protection circuit configured to generate the input control signal in response to a system input signal and a feedback voltage indicative of a voltage across the first and second power terminals of the power switch, the system input signal determining an on-period and off-period of the power switch, while the power switch is in an off state in response to the system input signal and in response to the feedback voltage e

Assignees

• Alpha & Omega Semiconductor Cayman Ltd

Inventors

• Tran Son
• Suh Bum-Seok
• Cho Wonjin

Classifications

• H05B6/062 Primary

  for cooking plates or the like · CPC title

• H03K5/19

  Monitoring patterns of pulse trains (indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02) · CPC title

• H03K17/0828

  in composite switches · CPC title

• H03K19/017509

  Interface arrangements · CPC title

• H03K17/168

  in composite switches · CPC title