Hybrid half/quarter-rate DFE

Patent metadata

Field	Value
Publication number	US-10476707-B2
Application number	US-201816058896-A
Country	US
Kind code	B2
Filing date	Aug 8, 2018
Priority date	Mar 5, 2018
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

First claim

What is claimed is:

1. A two-stage decision feedback equalizer for receiving serial data, at an analog input, at a first data rate,
the two-stage decision feedback equalizer comprising:
a first stage, comprising a half-rate predictive decision feedback equalizer having:
an analog input connected to the analog input of the two-stage decision feedback equalizer,
a first digital output, and
a second digital output; and

a second stage, comprising:
a first flip flop having a data input connected to the first digital output,
a second flip flop having a data input connected to the first digital output,
a third flip flop having a data input connected to the second digital output, and
a fourth flip flop having a data input connected to the second digital output,

the first stage being in a first clock domain configured to operate with a first clock at a frequency equal to one half of the first data rate, and
the second stage being in a second clock domain configured to operate with a second clock at a frequency equal to one quarter of the first data rate.

2. The two-stage decision feedback equalizer of claim 1 , wherein the first stage comprises current mode logic circuits.

3. The two-stage decision feedback equalizer of claim 1 , wherein the second stage comprises complementary metal oxide semiconductor circuits.

4. The two-stage decision feedback equalizer of claim 1 , wherein the first stage comprises:
a first path having an input connected to the analog input, and
a second path having an input connected to the analog input,
the first path being configured to generate, at the first digital output, a digital data value with every cycle of the first clock, during a portion of a time interval when the first clock is low; and
the second path being configured to generate, at the second digital output, a digital data value with every cycle of the first clock, during a portion of a time interval when the first clock is high.

5. The two-stage decision feedback equalizer of claim 1 , further comprising a phase control circuit configured to align transitions of a first phase of the second clock with transitions of a first phase of the first clock.

6. The two-stage decision feedback equalizer of claim 5 , wherein the phase control circuit comprises a fifth flip flop having:
a data input connected to the first phase of the first clock,
a clock input connected to the first phase of the second clock, and
an output.

7. The two-stage decision feedback equalizer of claim 6 , wherein the phase control circuit further comprises:
a phase interpolator, configured:
to receive:
two phases of the second clock, the two phases differing by more than 0 degrees and less than 180 degrees, and
a control signal; and

to form, as output, a signal having a phase corresponding to the control signal.

8. The two-stage decision feedback equalizer of claim 7 , further comprising a logic circuit having:
an input connected to the output of the fifth flip flop, and
an output connected to the phase interpolator, the logic circuit being configured to generate the control signal for the phase interpolator.

9. The two-stage decision feedback equalizer of claim 8 , wherein the logic circuit comprises an up-down counter, configured:
to increment a count value when the output of the fifth flip flop is high and
to decrement the count value when the output of the fifth flip flop is low.

10. The two-stage decision feedback equalizer of claim 1 , wherein the first flip flop has a clock input configured to receive a first phase of the second clock, the first phase of the second clock having a rising edge aligned with every other falling edge of the first clock.

11. The two-stage decision feedback equalizer of claim 10 , wherein the second flip flop has a clock input configured to receive a second phase of the second clock, the second phase of the second clock having a rising edge aligned with every falling edge of the first phase of the second clock.

12. The two-stage decision feedback equalizer of claim 11 , wherein the third flip flop has a clock input configured to receive a third phase of the second clock, the third phase of the second clock having a rising edge following each rising edge of the first phase of the second clock by one quarter cycle of the second clock.

13. The two-stage decision feedback equalizer of claim 12 , wherein the fourth flip flop has a clock input configured to receive a fourth phase of the second clock, the fourth phase of the second clock having a rising edge aligned with every falling edge of the third phase of the second clock.

14. A two-stage decision feedback equalizer for receiving serial data, at an analog input, at a first data rate,
the two-stage decision feedback equalizer comprising:
a first stage, connected to the analog input, the first stage comprising a half-rate predictive decision feedback equalizer comprising current mode logic circuits; and
a second stage, connected to the first stage, the second stage comprising complementary metal oxide semiconductor circuits,

the first stage being in a first clock domain configured to operate with a first clock at a frequency equal to one half of the first data rate, and
the second stage being in a second clock domain configured to operate with a second clock at a frequency equal to one quarter of the first data rate.

15. The two-stage decision feedback equalizer of claim 14 , wherein:
the half-rate predictive decision feedback equalizer of the first stage has:
an analog input connected to the analog input of the two-stage decision feedback equalizer,
a first digital output, and
a second digital output; and

the second stage comprises:
a first flip flop having a data input connected to the first digital output, and
a second flip flop having a data input connected to the first digital output.

16. The two-stage decision feedback equalizer of claim 15 , wherein the first stage comprises:
a first path having an input connected to the analog input, and
a second path having an input connected to the analog input,
the first path being configured to generate, at the first digital output, a digital data value with every cycle of the first clock, during a portion of a time interval when the first clock is low; and
the second path being configured to generate, at the second digital output, a digital data value with every cycle of the first clock, during a portion of a time interval when the first clock is high.

17. The two-stage decision feedback equalizer of claim 15 , further comprising a phase control circuit configured to align transitions of a first phase of the second clock with transitions of a first phase of the first clock.

18. The two-stage decision feedback equalizer of claim 17 , wherein the phase control circuit comprises a third flip flop having:
a data input connected to the first phase of the first clock,
a clock input connected to the first phase of the second clock, and
an output.

19. The two-stage decision feedback equalizer of claim 18 , wherein the phase control circuit further comprises:
a phase interpolator, configured:
to receive:
two phases of the second clock, the two phases differing by more than 0 degrees and less than 180 degrees, and
a control signal; and

to form, as output, a signal having a phase corresponding to the control signal.

20. A display, comprising:
a timing controller having a serial data output; and
a driver integrated circuit having an analog input for receiving

Assignees

• Samsung Display Co Ltd

Inventors

• Jose Anup P
• Amirkhany Amir
• Hekmat Mohammad

Classifications

• H03D7/1441

  using field-effect transistors (H03D7/145 takes precedence) · CPC title

• G09G2310/0264

  Details of driving circuits · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• H03M9/00 Primary

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title