Quarter-rate speculative decision feedback equalizer

Patent metadata

Field	Value
Publication number	US-9106461-B2
Application number	US-201213554763-A
Country	US
Kind code	B2
Filing date	Jul 20, 2012
Priority date	Jul 20, 2012
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

According to an aspect of an embodiment of the present disclosure, a method of relaxing a timing constraint associated with reducing inter-symbol interference (ISI) of input data includes adding an ISI cancellation value to input data received at a first clock rate to generate first speculative data. The method further includes subtracting the ISI cancellation value from the input data to generate second speculative data. The method also includes sampling the first speculative data and the second speculative data at a second clock rate that is one-fourth of the first clock rate such that a timing constraint associated with performing the ISI reduction is relaxed.

First claim

What is claimed is:

1. A system for relaxing a timing constraint associated with reducing inter-symbol interference (ISI) of input data, the system comprising:
a speculative analog circuit configured to:
receive input data at a first clock rate;
add an inter-symbol interference (ISI) cancellation value to the input data to generate first speculative data; and
subtract the ISI cancellation value from the input data to generate second speculative data; and

a sampling circui…

Assignees

• Parikh Samir
• Fujitsu Ltd

Inventors

• Parikh Samir

Classifications

• H04L25/03057 Primary

  Electricity · mapped topic