Clock and data recovery device and method using current-controlled oscillator

Patent metadata

Field	Value
Publication number	US-10476510-B2
Application number	US-201816025508-A
Country	US
Kind code	B2
Filing date	Jul 2, 2018
Priority date	Dec 5, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A clock and data recovery device associated with a data receiving apparatus, the clock and data recovery device including an oscillator configured to generate a clock signal; and a regulator configured to supply current to the oscillator, the regulator including, a first current source configured to supply a first current to the oscillator, and a second current source configured to supply a second current to the oscillator such that the second current is supplied to the oscillator, after a period of time, to de-emphasize the first current, the period of time being based on the first current.

First claim

What is claimed is:

1. A clock and data recovery device associated with a data receiving apparatus, comprising:
an oscillator configured to generate a clock signal; and
a regulator configured to supply current to the oscillator, the regulator including,
a first current source configured to supply a first current to the oscillator, and
a second current source configured to supply a second current to the oscillator such that the second current is supplied to the oscillator, after a period of time, to de-emphasize the first current, the period of time being based on the first current.

2. The clock and data recovery device of claim 1 , wherein the regulator comprises:
a third current source configured to supply a third current to the oscillator such that the third current is supplied to the oscillator before the period of time to pre-emphasize the first current.

3. The clock and data recovery device of claim 1 , further comprising:
a phase detector configured to receive incoming data and an output signal of the oscillator, and to output a control signal based on a phase of the incoming data and a phase of the output signal of the oscillator.

4. The clock and data recovery device of claim 3 , wherein the phase detector is configured to output a first control signal as the control signal when the phase of the incoming data is ahead of the phase of the output signal of the oscillator.

5. The clock and data recovery device of claim 4 , wherein the regulator is configured to receive the first control signal output from the phase detector, and to increase a frequency of the oscillator by supplying current to the oscillator based on the first control signal.

6. The clock and data recovery device of claim 4 , wherein the phase detector is configured to output a second control signal as the control signal when the phase of the output signal of the oscillator is ahead of the phase of the incoming data.

7. The clock and data recovery device of claim 6 , wherein the regulator is configured to receive the second control signal from the phase detector, and to decrease a frequency of the oscillator by supplying current to the oscillator based on the second control signal.

8. The clock and data recovery device of claim 3 , further comprising:
a charge pump configured to generate a voltage based on the control signal, and to output the voltage to the regulator to drive the regulator.

9. The clock and data recovery device of claim 8 , wherein the first current source comprises:
a first transistor controlled by the voltage of the charge pump, and
a second transistor controlled by the control signal from the phase detector.

10. The clock and data recovery device of claim 8 , wherein the clock and data recovery device is configured to generate a signal by delaying the control signal of the phase detector for a set period of time to generate a delayed control signal and inverting the delayed control signal to generate the signal, and the second current source comprises:
a first transistor controlled by the voltage of the charge pump, and
a second transistor controlled by the signal.

11. A clock and data recovery device associated with a data receiving apparatus, comprising:
an oscillator configured to generate a synchronized clock signal, the data receiving apparatus configured to receive incoming data based on the synchronized clock signal;
a variable capacitor configured to selectively adjust a frequency of the oscillator when the oscillator is operated at a frequency higher than a set frequency; and
a regulator configured to supply current to the oscillator, and to selectively adjust the frequency of the oscillator by adjusting the current supplied to the oscillator when the oscillator is operated at a frequency lower than the set frequency.

12. The clock and data recovery device of claim 11 , wherein the regulator comprises:
a first current source configured to supply a first current to the oscillator, and
a second current source configured to supply a second current to the oscillator such that the second current is supplied to the oscillator, after a period of time to de-emphasize, the period of time being based on the first current.

13. The clock and data recovery device of claim 12 , wherein the regulator comprises a third current source configured to supply a third current to the oscillator such that the third current is supplied before the period of time to pre-emphasize the first current.

14. The clock and data recovery device of claim 12 , further comprising:
a phase detector configured to receive the incoming data and an output signal of the oscillator, and to output a control signal based on a phase of the incoming data and a phase of the output signal of the oscillator.

15. The clock and data recovery device of claim 14 , wherein the phase detector is configured to output a first control signal as the control signal when the phase of the incoming data is ahead of the phase of the output signal of the oscillator.

16. The clock and data recovery device of claim 15 , wherein the regulator is configured to receive the first control signal from the phase detector, and to increase a frequency of the oscillator by supplying current to the oscillator based on the first control signal.

17. The clock and data recovery device of claim 15 , wherein the phase detector is configured to output a second control signal as the control signal when the phase of the output signal of the oscillator is ahead of the phase of the incoming data.

18. The clock and data recovery device of claim 17 , wherein the regulator is configured to receive the second control signal from the phase detector, and to decrease a frequency of the oscillator by supplying current to the oscillator based on the second control signal.

19. The clock and data recovery device of claim 14 , further comprising:
a charge pump configured to generate a voltage based on the control signal, and to output the voltage to the regulator to drive of the regulator.

20. The clock and data recovery device of claim 19 , wherein the first current source comprises:
a first transistor controlled by an output voltage from the charge pump, and
a second transistor controlled by the control signal from the phase detector.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Hwang Ho

Classifications

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title

• H03L7/0995 Primary

  the oscillator comprising a ring oscillator · CPC title

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title