Structures and operations of integrated circuits having network of configurable switches

Patent metadata

Field	Value
Publication number	US-10476492-B2
Application number	US-201816201915-A
Country	US
Kind code	B2
Filing date	Nov 27, 2018
Priority date	Nov 27, 2018
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

Embodiments herein may present an integrated circuit including a switch, where the switch together with other switches forms a network of switches to perform a sequence of operations according to a structure of a collective tree. The switch includes a first number of input ports, a second number of output ports, a configurable crossbar to selectively couple the first number of input ports to the second number of output ports, and a computation engine coupled to the first number of input ports, the second number of output ports, and the crossbar. The computation engine of the switch performs an operation corresponding to an operation represented by a node of the collective tree. The switch further includes one or more registers to selectively configure the first number of input ports and the configurable crossbar. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a switch having:
a first number of input ports;
a second number of output ports;
a configurable crossbar to selectively couple the first number of input ports to the second number of output ports;
a computation engine coupled to the first number of input ports, the second number of output ports, and the crossbar, to perform an operation and provide results of the operation to a first group of output ports of the second number of output ports; and
one or more registers to selectively configure the first number of input ports and the configurable crossbar, to enable the first number of input ports to selectively pass data to the computation engine to supply the computation engine with operands of the operation, and the computation engine to selectively route results of the operation to the first group of output ports of the second number of output ports, or to enable the first number of input ports to pass through data to a second group of output ports of the second number of output ports;

wherein the switch together with other switches forms a network of switches to perform a sequence of operations according to a structure of a collective tree, and the operation performed by the computation engine corresponds to an operation represented by a node of the collective tree.

2. The integrated circuit of claim 1 , wherein the computation engine is arranged to perform the operation when the operands of the operation are available from the first number of input ports, and further to route results of the operation to the first group of output ports.

3. The integrated circuit of claim 1 , wherein the one or more registers is further to configure one or more input ports of the first number of input ports neither to pass through data to the second group of output ports nor to supply the data as the operands to the computation engine.

4. The integrated circuit of claim 1 , wherein the first group of output ports includes only one output port to receive the results of the operation from the computation engine and not to receive data from the first number of input ports.

5. The integrated circuit of claim 1 , wherein the second group of output ports are to receive data from only the first number of input ports and not to receive the results of the operation from the computation engine.

6. The integrated circuit of claim 1 , wherein the operation to be performed by the computation engine includes a selected operation of a vector operation, a scalar operation, or a matrix operation.

7. The integrated circuit of claim 1 , wherein the computation engine includes a tree of arithmetic and logic units (ALU) to perform the operation.

8. The integrated circuit of claim 1 , wherein the computation engine includes a first register of the one or more registers to indicate input ports of the first number of input ports to supply the operands of the operation, and a second register to indicate the first group of output ports to route the results of the operation.

9. The integrated circuit of claim 1 , wherein an input port of the first number of input ports includes a configuration register to store a bit vector that indicates whether the input port is to pass through data to an output port of the second number of output ports, to supply the data as an operand in the operation to be performed by the computation engine, or neither to pass through the data nor to supply the data as the operand.

10. The integrated circuit of claim 9 , wherein the bit vector has a length equal to the second number plus 1, wherein a bit of the second number of bits of the bit vector corresponding to an output port of the second number of output ports, and the second number plus 1 bit of the bit vector represents whether the input port is to supply the data as the operand in the operation to be performed by the computation engine.

11. The integrated circuit of claim 9 , wherein the configuration register is a first register of the input port, and the input port further includes a second register to indicate the input port is to receive data from an output port of the second number of output ports.

12. An integrated circuit, comprising:
a plurality of switches, each switch including a first number of input ports and a second number of output ports selectively coupled to one or more of a number of input ports of one or more other switches to form a network of switches on a die;
wherein each switch further includes a computation engine configurable to be coupled to selected ones of the first number of input ports, and selected ones of the second number of output ports to perform an operation corresponding to a node of a collective tree, and the network of switches are configurable to jointly take on a network topology reflective of the collective tree, and performs a sequence of operations represented by the collective tree.

13. The integrated circuit of claim 12 , wherein each switch further includes:
one or more registers to selectively configure the first number of input ports, to enable the first number of input ports to selectively pass data to the computation engine to supply the computation engine with operands of the operation, and the computation engine to selectively route the results of the operation to a first group of output ports of the second number of output ports, or the first number of input ports to selectively pass through data to a second group of output ports of the second number of output ports.

14. The integrated circuit of claim 13 , wherein the computation engine is arranged to perform the operation when the operands of the operation are available from the first number of input ports.

15. The integrated circuit of claim 12 , wherein the switches are configurable such that at least one switch of a group of corresponding switches has one or more descendent switches corresponding to one or more nodes of the collective tree that are descendent nodes of the node to which the at least one switch corresponds, and wherein the computation engine of the at least one switch performs the operation represented by the node when descendent switches have performed operations represented by the descendent nodes.

16. The integrated circuit of claim 15 , wherein the switches are configurable such that at least one switch of the group of corresponding switches is a root switch corresponding to a root node of the collective tree, and the root switch is to perform an operation represented by the root node of the collective tree after all other switches of the group of corresponding switches have performed operations represented by all other nodes of the collective tree except the root node.

17. The integrated circuit of claim 16 , wherein the at least one switch configurable as the root switch is further configurable to broadcast a result of the operation performed by the root switch, to at least some of the other switches of the group of corresponding switches.

18. The integrated circuit of claim 12 , wherein the plurality of switches includes a first switch with the first number of input ports and the second number of output ports, and a second switch having a third number of input ports, and a fourth number of output ports, the first number is different from the third number, or the second number is different from the fourth number.

19. The integrated circuit of claim 12 , wherein the operation to be performed by the computation engine includes a selected operation of a vector operation, a scalar operation, or a matrix operation.

Assignees

• Intel Corp

Inventors

• More Ankit
• Howard Jason M
• Pawlowski Robert
• Petrini Fabrizio
• Smith Shaden

Classifications

• H03K17/005 Primary

  with several inputs only · CPC title

• H03K17/007

  with several outputs only · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• H03K19/1733 Primary

  Controllable logic circuits (H03K19/177 takes precedence) · CPC title