Decimation filter

Patent metadata

Field	Value
Publication number	US-10476483-B2
Application number	US-201715808157-A
Country	US
Kind code	B2
Filing date	Nov 9, 2017
Priority date	Nov 9, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

Filters are discussed where a first window function and a second window function are applied to a digital input signal, wherein a window length of the first window function is longer than a window length of the second window function. The results of this windowing are integrated.

First claim

What is claimed is:

1. A device, comprising:
a windowing circuit configured to apply a first window function to a first digital signal to generate a second digital signal and to apply a second window function to the first digital signal to generate a third digital signal, wherein a window length of the first window function is longer than a window length of the second window function,
a first integrator configured to receive the second digital signal,
a second integrator configured to receive the third digital signal,
an analog-to-digital converter configured to output the first digital signal based on a received analog signal,
a chopping circuit configured to apply a chopping signal at an input of the analog-to-digital converter and at an output of the second integrator, and
an offset compensation circuit configured to estimate an offset of the first digital signal based on an output signal of the second integrator and the applied chopping signal, and to compensate the estimated offset in an output signal of the first integrator.

2. The device of claim 1 , wherein the window length of the first window function is an integer multiple of the window length of the second window function.

3. The device of claim 1 , wherein a sampling rate of a fourth digital signal output by the first integrator and a fifth digital signal output by the second integrator is lower than a sampling rate of the first digital signal.

4. The device of claim 1 , wherein at least one of the first window function and the second window function is selected from the group consisting of a Tuckey window, a Hamming window or a Hanning window.

5. The device of claim 1 , wherein the windowing circuit comprises a window function generator configured to generate at least one of the first window function and the second window function based on an interpolation between stored coefficients.

6. The device of claim 1 , wherein the windowing circuit comprises a window function generator configured to generate the second window function, wherein the windowing circuit is configured to apply the first window function by:
applying a first part of the second window function to generate first samples of the second digital signal, followed by
scaling samples of the first digital signal by a maximum value of the second window function to generate second samples of the second digital signal following the first samples, followed by
applying a second part of the second window function to generate third samples of the second digital signal following the second samples.

7. The device of claim 6 , wherein the windowing circuit further comprises a multiplier, wherein a first input of the multiplier is arranged to receive the first digital signal, wherein a second input of the multiplier is coupled to an output of the window function generator, and wherein an output of the multiplier is coupled to an input of the second integrator and to a first input of a multiplexer, wherein a second input of the multiplexer is arranged to receive the first digital signal, and wherein an output of the multiplexer is coupled to an input of the first integrator.

8. The device of claim 1 , further comprising an evaluation circuit configured to control a further device based on an output of the first integrator and to detect a malfunction based on an output of the second integrator.

9. The device of claim 1 , wherein the offset compensation circuit is configured to perform an averaging of the estimated offset.

10. The device of claim 1 , wherein the offset compensation circuit is configured to estimate a slew rate of the output signal of the second integrator and to estimate the offset based on the estimated slew rate.

11. A device, comprising:
a first decimation path configured to provide a first decimated signal based on an input signal,
a second decimation path configured to provide a second decimated signal based on the input signal, wherein the second decimation path has a faster response to a change in the input signal than the first decimation path, and
an offset compensation circuit configured to estimate an offset of the input signal by applying chopping to the second decimation path and to compensate the estimated offset in the first decimation path.

12. The device of claim 11 , further comprising an analog-to-digital converter configured to provide the input signal, wherein the offset compensation circuit is configured to apply a chopping signal at an input of the analog-to-digital converter and at an output of the second decimation path.

13. The device of claim 12 , wherein:
the first decimation path comprises a first integrator;
the second decimation path comprises a second integrator; and
the offset compensation circuit is further configured to estimate the offset of the input signal based on an output signal of the second integrator and the applied chopping signal, and to compensate the estimated offset in an output signal of the first integrator.

14. The device of claim 11 , wherein the offset compensation circuit is configured to estimate a slew rate of an output signal of the second decimation path and to estimate the offset based on the slew rate.

15. A method, comprising:
converting an analog signal to a first digital signal,
applying a first window function to the first digital signal to generate a second digital signal,
applying a second window function to the first digital signal to generate a third digital signal, wherein a window length of the second window function is shorter than a window length of the first window function,
integrating the second digital signal or a signal derived therefrom to generate a fourth digital signal,
integrating the third digital signal or a signal derived therefrom to generate a fifth digital signal,
applying a chopping signal to the analog signal and to the fifth digital signal,
estimating an offset of the first digital signal based on the fifth digital signal and the applied chopping signal, and
compensating the estimated offset in the fourth digital signal.

16. The method of claim 15 , wherein the window length of the first window function is an integer multiple of the window length of the second window function.

17. The method of claim 15 , further comprising generating at least one of the first window function and the second window function based on an interpolation between stored coefficients.

18. The method of claim 15 , wherein applying the first window function comprises:
applying a first part of the second window function to generate first samples of the second digital signal, followed by
scaling samples of the first digital signal by a maximum value of the second window function to generate second samples of the second digital signal following the first samples, followed by
applying a second part of the second window function to generate third samples of the second digital signal following the second samples.

19. The method of claim 15 , further comprising:
activating the chopping signal of said estimating step, and
deactivating the chopping signal when using the offset compensated fourth digital signal.

Assignees

• Infineon Technologies Ag

Inventors

• Straeussnigg Dietmar
• Bogner Peter
• Kropfitsch Michael
• Barrenscheen Jens

Classifications

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H02P27/08

  with pulse width modulation · CPC title

• H03M3/462

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03H17/0276

  having two phases · CPC title

• H03H17/0664 Primary

  where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation · CPC title