Dynamically adjustable decimation filter circuitry

Patent metadata

Field	Value
Publication number	US-9837988-B1
Application number	US-201514669501-A
Country	US
Kind code	B1
Filing date	Mar 26, 2015
Priority date	Mar 26, 2015
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

Decimation filter circuitry may include polyphase filtering structures that perform decimation filtering using filter coefficients. Generic polyphase filtering structures do not take advantage of symmetries between the corresponding filter coefficients. If desired, the arrangement of the polyphase filtering structures in the decimation filter circuitry may be optimized relative to generic polyphase filtering structures to take advantage of corresponding filter coefficient symmetries, thereby allowing for implementation of dynamic decimation ratios and a dynamic number of channels while reducing the number of required multipliers by half with respect to generic polyphase filters. Decimation filters may include pre-adder circuitry that receives first and second portions of a data stream and adds corresponding samples from the first and second portions to generate pre-added values. Convolving circuitry may generate filtered output data by convolving the pre-added values with corresponding filter coefficients based on symmetry of the filter coefficients.

First claim

What is claimed is:

1. Decimation filter circuitry, comprising:
data buffer circuitry that receives and reorders first and second portions of a data stream in respective first and second buffers, wherein the first portion of the data stream is loaded in the first buffer according to a first ordering, and wherein the second portion of the data stream is loaded in the second buffer according to a second ordering that is different from the first ordering;
pre-adder circuitry that is adapted to receive the reordered first and second portions of the data stream and to add corresponding data samples from the reordered first and second portions of the data stream to generate a plurality of pre-added values;
memory that is configured to store a plurality of decimation filter coefficient values;
address control circuitry that is configured to identify a selected decimation ratio and a selected subset of the plurality of decimation filter coefficient values corresponding to the selected decimation ratio; and
dot-product circuitry, the address control circuitry being configured to control the memory to provide the selected subset of the plurality of decimation filter coefficient values to the dot-product circuitry, and the dot-product circuitry being configured to generate filtered output data by convolving the plurality of pre-added values with the selected subset of the plurality of decimation filter coefficient values provided by the memory.

2. The decimation filter circuitry defined in claim 1 , wherein the pre-adder circuitry adds a first data sample from the first portion with a first data sample from the second portion to generate a first pre-added value and adds a second data sample form the first portion with a second data sample from the second portion to generate a second pre-added value.

3. The decimation filter circuitry defined in claim 2 , wherein the dot-product circuitry comprises:
multiplier circuitry that generates a first multiplied value by multiplying the first pre-added value by a first decimation filter coefficient value of the plurality of decimation filter coefficient values and that generates a second multiplied value by multiplying the second pre-added value by a second decimation filter coefficient value of the plurality of decimation filter coefficient values.

4. The decimation filter circuitry defined in claim 3 , wherein the dot-product circuitry further comprises:
summing circuitry that generates a summed value by summing the first and second multiplied values.

5. The decimation filter circuitry defined in claim 4 , further comprising:
adder circuitry that adds a selected one of a logic “0” value and a data sample from a third portion of the data stream to the summed value.

6. The decimation filter circuitry defined in claim 5 , wherein the data stream comprises a plurality of data stream phases, further comprising:
accumulator circuitry that generates accumulated filtered output data by accumulating the summed value and additional summed values each corresponding to a respective one of the plurality of data stream phases.

7. The decimation filter circuitry defined in claim 1 , wherein the first and second buffers comprise respective first and second sets of columns, and wherein the decimation filter circuitry further comprises:
data buffering circuitry that receives the data stream and partitions the data stream into the first and second portions, wherein the first ordering fills the first set of columns in the first buffer in a first direction, and wherein the second ordering fills the second set of columns in the second buffer in a second direction that is opposite the first direction.

8. The decimation filter circuitry defined in claim 7 , wherein the data buffering circuitry comprises:
a first data buffer circuit;
a second data buffer circuit; and
a center data buffer circuit interposed between the first and second data buffer circuits.

9. The decimation filter circuitry defined in claim 8 , wherein the first, second, and center buffer circuits format and reorder the data stream so that the first and second portions of the data stream are aligned with the plurality of decimation filter coefficient values.

10. A decimation filter operable to receive a data stream, the decimation filter comprising:
a first buffer circuit configured to store and format a first portion of the received data stream;
a selector circuit;
convolving circuitry coupled to an output of the selector circuit, the first buffer circuit being configured to convey the stored first portion of the received data stream to the convolving circuitry via the selector circuit;
a center buffer circuit configured to re-order a second portion of the received data stream;
a second buffer circuit, the center buffer circuit being interposed between the first and second buffer circuits and the second buffer circuit being configured to store and format the re-ordered second portion of the received data stream, wherein the stored re-ordered second portion of the received data stream exhibits a symmetry about the center buffer circuit with respect to the stored first portion of the received data stream; and
a combining circuit, wherein the first buffer circuit is configured to convey the stored first portion of the received data stream to the convolving circuitry via the combining circuit and the selector circuit.

11. The decimation filter defined in claim 10 , wherein the convolving circuitry is configured to generate a filtered data output by convolving the stored first portion and the stored reordered second portion of the received data stream with a plurality of filter coefficient values based on the symmetry, wherein the received data stream has a first sample rate and the filtered data output has a second sample rate that is less than or equal to the first sample rate.

12. The decimation filter defined in claim 11 , wherein the convolving circuitry comprises pre-addition circuitry that adds data samples from the stored first portion of the received data stream with corresponding samples from the stored reordered second portion of the received data stream based on the symmetry.

13. The decimation filter defined in claim 10 , further comprising:
an additional combining circuit; and
an additional selector circuit, wherein the second buffer circuit conveys the stored re-ordered second portion of the received data stream to the convolving circuitry via the additional combining circuit and the additional selector circuit.

14. The decimation filter defined in claim 10 , further comprising:
an additional selector circuit; and
a multiplexing circuit, wherein the first buffer circuit conveys a third portion of the received data stream to the convolving circuitry via the combining circuit, the additional selector circuit, and the multiplexing circuit.

15. The decimation filter defined in claim 14 , wherein the convolving circuitry further comprises adder circuitry, wherein the adder circuitry adds the third portion of the received data stream to the filtered data output.

16. The decimation filter defined in claim 10 , wherein the first buffer circuit has a first input and a first output, the center buffer circuit has a second input and a second output, and the second buffer circuit has a third input and a third output, further comprising:
a first additional selector circuit coupled between the first output and the second input;
a second additional selector circuit coupled between the first output and the first input; and
a third additional selector circuit coupled between the third output and the

Assignees

• Altera Corp

Inventors

• Cheung Colman C

Classifications

• H03H17/0248 Primary

  Filters characterised by a particular frequency response or filtering method · CPC title

• H03H17/0664 Primary

  where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation · CPC title