Display panel, its manufacturing method, and display device

Patent metadata

Field	Value
Publication number	US-10475824-B2
Application number	US-201815972096-A
Country	US
Kind code	B2
Filing date	May 4, 2018
Priority date	Jul 11, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

The present disclosure provides a display panel, its manufacturing method and a display device. The manufacturing method of the display panel comprises: forming, on a substrate, a thin film transistor comprising a gate electrode, an active layer, a source electrode and a drain electrode; forming a hydrogen diffusion barrier layer that covers the entire substrate, wherein the hydrogen diffusion barrier layer is electrically conductive and is electrically connected to the drain electrode; and forming a photosensitive structure layer on the hydrogen diffusion barrier layer.

First claim

What is claimed is:

1. A method for manufacturing a display panel, comprising steps of:
forming, on a substrate, a thin film transistor comprising a gate electrode, an active layer, a source electrode and a drain electrode;
forming a hydrogen diffusion barrier layer that covers the entire substrate, wherein the hydrogen diffusion barrier layer is electrically conductive and is electrically connected to the drain electrode; and
forming a photosensitive structure layer on the hydrogen diffusion barrier layer, wherein the step of forming the photosensitive structure layer on the hydrogen diffusion barrier layer comprises:
depositing an N-type amorphous silicon thin film on the hydrogen diffusion barrier layer by adopting a plasma enhanced chemical vapor deposition process;
depositing an intrinsic amorphous silicon thin film on the N-type amorphous silicon thin film; and
subjecting the intrinsic amorphous silicon thin film to ion implantation, and subjecting the ion-implanted intrinsic amorphous silicon thin film to activation treatment to form a P-type amorphous silicon thin film on an upper layer of the intrinsic amorphous silicon thin film.

2. The method according to claim 1 , further comprising:
depositing a first conductive thin film on the photosensitive structure layer; and
patterning the hydrogen diffusion barrier layer, the photosensitive structure layer and the first conductive thin film to form a photodiode consisting of a barrier electrode formed by the hydrogen diffusion barrier layer, a photosensitive structure formed by the photosensitive structure layer and a first electrode formed by the first conductive thin film.

3. The method according to claim 2 , further comprising:
forming a planarization layer after the patterning, wherein the planarization layer has a via hole that runs through the planarization layer to expose the first electrode; and
forming, on the planarization layer, a second electrode that is electrically connected to the first electrode through the via hole.

4. The method according to claim 3 , further comprising forming a light-shielding layer on the planarization layer, wherein an orthogonal projection of the light-shielding layer on the substrate covers an orthogonal projection of a channel area on the substrate.

5. The method according to claim 4 , wherein the light-shielding layer and the second electrode are formed simultaneously.

6. The method according to claim 3 , further comprising forming, on the second electrode, an electrode lead that is electrically connected to the second electrode.

7. The method according to claim 1 , wherein the hydrogen diffusion barrier layer comprises a first material layer, a second material layer and a third material layer stacked one on another, wherein the first material layer and the third material layer comprise indium tin oxide, and the second material layer comprises silver.

8. The method according to claim 1 , wherein the active layer comprises indium gallium zinc oxide or indium tin zinc oxide.

9. The method according to claim 1 , wherein the step of forming the thin film transistor on the substrate comprises:
forming, on the substrate, the gate electrode and a signal line, and a first insulating layer covering the gate electrode and the signal line;
forming the active layer on the first insulating layer, wherein the active layer is an oxide active layer;
forming a second insulating layer covering the oxide active layer, wherein the second insulating layer has two first via holes that run through the second insulating layer to expose the oxide active layer, and a second via hole that runs through the first insulating layer and the second insulating layer to expose the signal line;
forming the source electrode, the drain electrode and a connecting electrode on the second insulating layer, wherein the source electrode and the drain electrode are electrically connected to the oxide active layer through the two first via holes, respectively, and the connecting electrode is electrically connected to the signal line through the second via hole; and
forming a third insulating layer covering the source electrode, the drain electrode and the connecting electrode, wherein the third insulating layer has a third via hole that runs through the third insulating layer to expose the drain electrode, and a fourth via hole that runs through the third insulating layer to expose the connecting electrode.

10. The method according to claim 9 , wherein the hydrogen diffusion barrier layer comprises a first material layer, a second material layer and a third material layer stacked one on another, wherein the first material layer and the third material layer comprise indium tin oxide, and the second material layer comprises silver.

11. The method according to claim 9 , wherein the active layer comprises indium gallium zinc oxide or indium tin zinc oxide.

12. The method according to claim 1 , wherein the step of forming the thin film transistor on the substrate comprises:
forming, on the substrate, the gate electrode and a first insulating layer covering the gate electrode;
forming the active layer on the first insulating layer, wherein the active layer is an oxide active layer;
forming the source electrode and the drain electrode on the oxide active layer;
forming a third insulating layer covering the source electrode and the drain electrode, wherein the third insulating layer has a third via hole that runs through the third insulating layer to expose the drain electrode.

13. The method according to claim 12 , wherein the hydrogen diffusion barrier layer comprises a first material layer, a second material layer and a third material layer stacked one on another, wherein the first material layer and the third material layer comprise indium tin oxide, and the second material layer comprises silver.

14. The method according to claim 12 , wherein the active layer comprises indium gallium zinc oxide or indium tin zinc oxide.

15. A display panel manufactured by the method according to claim 1 and configured for fingerprint identification or X-ray detection.

16. A display device, comprising the display panel according to claim 15 .

17. The method according to claim 1 , further comprising:
patterning the hydrogen diffusion barrier layer to form the barrier electrode after forming the photosensitive structure layer on the hydrogen diffusion barrier layer by adopting the plasma enhanced chemical vapor deposition process.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Ren Qingrong
• Lee Woobong
• Wang Fengchao
• Sun Jianming
• Liu Yingwei
• Yang Wei
• Li Dongsheng

Classifications

• H01L27/1262

  Electricity · mapped topic

• H01L27/14636

  Electricity · mapped topic

• H01L31/022475

  Electricity · mapped topic

• H01L27/14685

  Electricity · mapped topic

• H01L27/124 Primary

  Electricity · mapped topic