TFT array substrate, display device including the same, and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10475817-B2
Application number	US-201815971435-A
Country	US
Kind code	B2
Filing date	May 4, 2018
Priority date	Jun 13, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A thin-film transistor (TFT) array substrate is provided. The TFT array substrate includes a base substrate, a semiconductor layer disposed on the base substrate, an insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the insulating layer. A top surface of a portion of the insulating layer overlapping the semiconductor layer in a plan view of the base substrate and a top surface of the gate electrode are placed on the same level.

First claim

What is claimed is:

1. A thin-film transistor (TFT) array substrate, comprising:
a base substrate;
a semiconductor layer disposed on the base substrate;
an insulating layer disposed on the semiconductor layer; and
a gate electrode disposed on the insulating layer,
wherein a top surface of a portion of the insulating layer overlapping the semiconductor layer in a plan view of the base substrate and a top surface of the gate electrode are placed on a same level,
the insulating layer covers the semiconductor layer, and
a side surface of the gate electrode faces a side surface of the semiconductor layer.

2. The TFT array substrate of claim 1 , wherein in the plan view of the base substrate, the gate electrode and the semiconductor layer are disposed not to overlap each other.

3. The TFT array substrate of claim 1 , wherein in the plan view of the base substrate, a thickness of a portion of the insulating layer overlapped by the gate electrode is greater than a thickness of the portion of the insulating layer overlapping the semiconductor layer.

4. The TFT array substrate of claim 1 , wherein in the plan view of the base substrate, a top surface of a portion of the insulating layer overlapped by the gate electrode is rougher than the top surface of the portion of the insulating layer overlapping the semiconductor layer.

5. The TFT array substrate of claim 1 , wherein the gate electrode includes a first gate electrode disposed adjacent to one sidewall of the semiconductor layer and a second gate electrode disposed adjacent to the other sidewall of the semiconductor layer.

6. The TFT array substrate of claim 1 , wherein the top surface of the portion of the insulating layer overlapping the semiconductor layer and the top surface of the gate electrode have a same roughness.

7. The TFT array substrate of claim 1 , wherein a height from a top surface of the base substrate to a highest top surface of the insulating layer is the same as a height from the top surface of the base substrate to the top surface of the portion of the insulating layer overlapping the semiconductor layer.

8. The TFT array substrate of claim 1 , wherein
the gate electrode includes first and second sub-gate electrodes spaced apart from each other,
the first sub-gate electrode is disposed adjacent to one side of the semiconductor layer, and
the second sub-gate electrode is disposed adjacent to the other side of the semiconductor layer.

9. The TFT array substrate of claim 8 , further comprising:
a source electrode placed in contact with the semiconductor layer via a first contact hole, which is formed to penetrate the insulating layer; and
a drain electrode placed in contact with the semiconductor layer via a second contact hole, which is formed to penetrate the insulating layer,
wherein electrical connections between the source and drain electrodes are controlled by both the first and second sub-gate electrodes.

10. The TFT array substrate of claim 1 , further comprising:
a buffer layer disposed between the base substrate and the semiconductor layer,
wherein in the plan view of the base substrate, a thickness of a portion of the buffer layer overlapped by the semiconductor layer is greater than a thickness of a portion of the buffer layer not overlapped by the semiconductor layer.

11. The TFT array substrate of claim 10 , wherein the buffer layer and the semiconductor layer have a same pattern.

12. The TFT array substrate of claim 10 , wherein a top surface of a portion of the insulating layer not overlapped by the semiconductor layer and a bottom surface of the semiconductor layer are placed on a same level.

13. The TFT array substrate of claim 1 , further comprising:
a source electrode placed in contact with the semiconductor layer via a first contact hole, which is formed to penetrate the insulating layer; and
a drain electrode placed in contact with the semiconductor layer via a second contact hole, which is formed to penetrate the insulating layer,
wherein the source electrode, the drain electrode, the semiconductor layer, and the gate electrode form a TFT.

14. The TFT array substrate of claim 13 , wherein
the semiconductor layer includes a source region, a drain region, and a channel region,
the source region is a doped region connected to the source electrode,
the drain region is a doped region connected to the drain electrode, and
the channel region is a region other than the source region and the drain region.

15. The TFT array substrate of claim 13 , wherein channels of the TFT are formed along sidewalls of the semiconductor layer that are adjacent to the gate electrode.

16. A display device, comprising:
a substrate; and
a plurality of pixels arranged in an array on the substrate and including at least one TFT,
wherein the TFT includes a semiconductor layer disposed on the substrate, an insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the insulating layer,
a top surface of a portion of the insulating layer overlapping the semiconductor layer and a top surface of the gate electrode are placed on a same level,
the insulating layer covers the semiconductor layer, and
a side surface of the gate electrode faces a side surface of the semiconductor layer.

17. A method of manufacturing a TFT array substrate, comprising:
forming a semiconductor layer on a base substrate;
forming an insulating layer on the semiconductor layer;
forming a gate electrode on the insulating layer; and
forming a source electrode and a drain electrode on the insulating layer,
wherein the forming of the gate electrode comprises depositing a gate electrode material layer on the insulating layer, forming a gate electrode pattern layer by patterning the gate electrode material layer, and polishing the gate electrode pattern layer through chemical mechanical polishing (CMP),
the insulating layer covers the semiconductor layer, and
a side surface of the gate electrode faces a side surface of the semiconductor layer.

18. The method of claim 17 , wherein the polishing of the gate electrode pattern layer comprises polishing the gate electrode pattern layer until a top surface of a portion of the insulating layer overlapping the semiconductor layer is exposed.

19. The method of claim 17 , wherein the forming of the gate electrode comprises, between the forming of the gate electrode pattern layer and the polishing of the gate electrode pattern layer, doping the semiconductor layer with impurities.

20. The method of claim 17 , further comprising:
forming a buffer layer having a pattern the same as that of the semiconductor layer on the base substrate before the forming of the semiconductor layer.

21. A thin-film transistor (TFT) array substrate, comprising:
a base substrate;
a semiconductor layer disposed on the base substrate;
an insulating layer disposed on the semiconductor layer; and
a gate electrode disposed on the insulating layer,
wherein the gate electrode and the semiconductor layer are disposed not to overlap each other in a plan view of the base substrate, and
the gate electrode is disposed adjacent to the semiconductor layer and overlaps the semiconductor layer in a direction parallel to a top surface of the base substrate.

22. The TFT array substrate of claim 21 , wherein a top surface of a portion of the insulating layer overlapping the semiconductor layer in the plan view of the base substrate and a top surface of the gate electrode ar

Assignees

• Samsung Display Co Ltd

Inventors

• Choo Byoung Kwon
• Bae Joon Hwa
• Cho Hyun Jin
• Cheon Jun Hyuk
• Yoon Zi Yeon
• Cho Woo Jin
• Choi Sung Hwan
• Choi Jeong Hye

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• G02F1/136213

  Storage capacitors associated with the pixel electrode · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• H01L21/3212

  Electricity · mapped topic