Semiconductor memory device including stacked body with conductivity and insulating members and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10475806-B2
Application number	US-201815907922-A
Country	US
Kind code	B2
Filing date	Feb 28, 2018
Priority date	Sep 7, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A semiconductor memory device includes a substrate with a first insulating film thereon, a wiring in the first insulating film, a first electrode film on the first insulating film, a stacked body on the first electrode film, made of alternating second insulating films and second electrode films, a first insulating member extending in a direction to penetrate the stacked body, a first semiconductor film around the first insulating member and connected to the first electrode film, a third insulating film around the first semiconductor film, a first conductive member extending in the direction to penetrate the stacked body and the first electrode film, and connected to the wiring, and a fourth insulating film around the first conductive member. The fourth insulating film has the same film structure as the third insulating film.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a first insulating film on a semiconductor substrate;
a first wiring in the first insulating film;
a first electrode film on the first insulating film;
a stacked body on the first electrode film and comprising second insulating films and second electrode films alternately stacked along a first direction;
a first insulating member penetrating the stacked body in the first direction to the first electrode film;
a first semiconductor film covering an outer surface of the first insulating member and electrically connected to the first electrode film;
a third insulating film covering an outer surface of the first semiconductor film;
a first conductive member extending in the first direction and penetrating the stacked body and the first electrode film, the first conductive member being electrically connected to the first wiring;
a fourth insulating film covering an outer surface of the first conductive member; and
a second semiconductor film between the first conductive member and the fourth insulating film, wherein
the fourth insulating film and the third insulating film have a same film structure, and
the first semiconductor film and the second semiconductor film have a same composition.

2. The semiconductor memory device according to claim 1 , wherein an end portion of the stacked body in a second direction crossing the first direction has a stair-stepped shape with a terrace portion for each of the second electrode films.

3. The semiconductor memory device according to claim 2 , further comprising:
a fifth insulating film covering the end portion of the stacked body; and
a second conductive member extending in the first direction, penetrating the fifth insulating film and connected to one second electrode film at the terrace portion, wherein
the first conductive member has the same composition as the second conductive member.

4. The semiconductor memory device according to claim 1 , wherein the first conductive member is a cylindrical shape.

5. The semiconductor memory device according to claim 1 , further comprising:
a second insulating member in the stacked body and extending in the second direction crossing the first direction, wherein
the first conductive member is between the first semiconductor film and the second insulating member in a third direction crossing a plane including the first and second directions.

6. A semiconductor memory device, comprising:
a first insulating film on a semiconductor substrate;
a first wiring in the first insulating film;
a first electrode film on the first insulating film;
a stacked body on the first electrode film and comprising second insulating films and second electrode films alternately stacked along a first direction;
a first insulating member penetrating the stacked body in the first direction to the first electrode film;
a first semiconductor film covering an outer surface of the first insulating member and electrically connected to the first electrode film;
a third insulating film covering an outer surface of the first semiconductor film;
a first conductive member extending in the first direction and penetrating the stacked body and the first electrode film, the first conductive member being electrically connected to the first wiring; and
a fourth insulating film covering an outer surface of the first conductive member, wherein
the fourth insulating film and the third insulating film have a same film structure,
the third insulating film includes:
a first insulating layer in contact with the first semiconductor film;
a second insulating layer covering an outer surface of the first insulating layer; and
a third layer between the first insulating layer and the second insulating layer, the fourth insulating film includes:
a fourth insulating layer;
a fifth insulating layer covering an outer surface of the fourth insulating layer; and
a sixth layer provided between the fourth insulating layer and the fifth insulating layer,

the first insulating layer has the same composition as the fourth insulating layer,
the second insulating layer has the same composition as the fifth insulating layer, and
the third layer has the same composition as the sixth layer.

7. The semiconductor memory device according to claim 6 , wherein the third layer between the first insulating layer and the second insulating layer is a charge storage layer.

8. The semiconductor memory device according to claim 6 , wherein
the first insulating layer has a thickness that is the same as a thickness of the fourth insulating layer,
the second insulating layer has a thickness that is a same as a thickness of the fifth insulating layer, and
the third layer has a thickness that is the same thickness as a thickness of the sixth layer.

Assignees

• Toshiba Memory Corp

Inventors

• Yagi Mikiko
• Takekida Hideto
• Yamanaka Takaya
• Mizutani Masaharu
• Wada Hideo

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H01L23/528

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L21/768

  Electricity · mapped topic