Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells

Patent metadata

Field	Value
Publication number	US-10475737-B2
Application number	US-201815900188-A
Country	US
Kind code	B2
Filing date	Feb 20, 2018
Priority date	Apr 12, 2011
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

First claim

The invention claimed is:

1. Integrated circuitry comprising a stack of horizontally extending and vertically overlapping conductive transistor gate lines, the integrated circuitry comprising:
a primary portion and an end portion, at least some of the gate lines extending farther in the horizontal direction in the end portion moving deeper into the stack in the end portion;
operative structures extending vertically through the gate lines in the primary portion, the operative structures comprising semiconductive material, the semiconductive material of the operative structures comprising interconnected channels of a plurality of vertically oriented transistors that individually comprise individual of the gate lines; and
dummy structures extending vertically through the gate lines in the end portion.

2. The stack of claim 1 further comprising contacts in the end portion that individual extend to the individual gate lines.

3. The integrated circuitry of claim 1 wherein the vertically oriented transistors are charge storage transistors of individual memory cells.

4. The integrated circuitry of claim 3 wherein the memory cells comprise a portion of NAND architecture.

5. The integrated circuitry of claim 1 wherein the operative and dummy structures comprise the same material.

6. The integrated circuitry of claim 5 wherein the operative and dummy structures comprise a plurality of the same materials.

7. The integrated circuitry of claim 6 wherein the same materials are arranged in the same lateral order relative one another in the operative and dummy structures.

8. The integrated circuitry of claim 5 wherein the operative and dummy structures consist essentially of the same material.

9. The integrated circuitry of claim 1 wherein the dummy structures comprise semiconductor material.

10. The integrated circuitry of claim 1 wherein the dummy structures comprise the semiconductive material.

11. A stack of horizontally extending and vertically overlapping features, the stack comprising:
a primary portion and an end portion, at least some of the features extending farther in the horizontal direction in the end portion moving deeper into the stack in the end portion;
operative structures extending vertically through the features in the primary portion; and
dummy structures extending vertically through the features in the end portion, the dummy structures individually comprising a cylinder of semiconductive material.

12. The stack of claim 11 comprising solid material filling radially internal regions of individual of the cylinders of semiconductive material.

13. The stack of claim 11 wherein individual of the cylinders of semiconductive material define a radially-outermost horizontal periphery of individual of the dummy structures.

14. The stack of claim 11 wherein the operative structures individually comprise a cylinder of semiconductor material.

15. The stack of claim 11 further comprising vertical contacts in the end portion connecting with conductive material of individual of the features.

16. A stack of horizontally extending and vertically overlapping features, the stack comprising:
a primary portion and an end portion, at least some of the features extending farther in the horizontal direction in the end portion moving deeper into the stack in the end portion;
operative structures extending vertically through the features in the primary portion, the operative structures comprising portions of memory cells, the memory cells comprising a portion of NAND architecture, the operative structures comprising interconnected channel regions of a NAND string; and
dummy structures extending vertically through the features in the end portion, some of the dummy structures horizontally overlapping the primary portion and the end portion.

17. The stack of claim 16 wherein the dummy structures comprise a cylinder of semiconductive material.

18. A stack of horizontally extending and vertically overlapping features, the stack comprising:
a primary portion and an end portion, at least some of the features extending farther in the horizontal direction in the end portion moving deeper into the stack in the end portion;
operative structures extending vertically through the features in the primary portion, the operative structures comprising portions of memory cells, the memory cells comprising a portion of NAND architecture, the operative structures comprising interconnected channel regions of a NAND string, at least some of the features comprising control gate lines;
dummy structures extending vertically through the control gate lines in the end portion; and
vertical contacts in the end portion connecting with individual of the control gate lines, the contacts and dummy structures having different horizontal cross-sections relative one another.

19. The stack of claim 18 wherein the different horizontal cross-sections are of the same shape and of different sizes relative one another.

20. The stack of claim 18 wherein the different horizontal cross-sections have different values of total horizontal area relative one another.

21. A stack of horizontally extending and vertically overlapping features, the stack comprising:
a primary portion and an end portion, at least some of the features extending farther in the horizontal direction in the end portion moving deeper into the stack in the end portion;
operative structures extending vertically through the features in the primary portion, the operative structures comprising portions of memory cells, the memory cells comprising a portion of NAND architecture, the operative structures comprising interconnected channel regions of a NAND string, the at least some of the features comprising control gate lines;
dummy structures extending vertically through the control gate lines in the end portion, some of the dummy structures being longitudinally spaced alone a horizontal line; and
vertical contacts in the end portion connecting with individual of the control gate lines, at least one of the vertical contacts being longitudinally between two immediately-longitudinally adjacent of the dummy structures in the horizontal line.

22. The stack of claim 21 wherein the horizontal line is linearly straight.

Assignees

• Micron Technology Inc

Inventors

• Tang Sanh D
• Lindsay Roger W
• Parat Krishna K

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C2213/11

  Metal ion trapping, i.e. using memory material including cavities, pores or spaces in form of tunnels or channels wherein metal ions can be trapped but do not react and form an electro-deposit creating filaments or dendrites · CPC title