Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components, and methods of forming an array of memory cells

Patent metadata

Field	Value
Publication number	US-9929175-B2
Application number	US-201715397919-A
Country	US
Kind code	B2
Filing date	Jan 4, 2017
Priority date	Apr 12, 2011
Publication date	Mar 27, 2018
Grant date	Mar 27, 2018

Abstract

A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

First claim

The invention claimed is:

1. A memory array comprising a stack of memory cells of NAND architecture:
a substrate comprising a primary portion and an end portion;
a plurality of NAND strings of vertically oriented transistors in the primary portion; the transistors individually comprising a channel, a tunnel dielectric laterally outward of the channel, a charge trapping material laterally outward of the tunnel dielectric, a dielectric material laterally outward of the charge trapping material, and a control gate laterally outward of the dielectric material; the control gate comprising a portion of one of a plurality of horizontally extending control gate lines, the control gate lines extending horizontally farther in the end portion moving deeper into the stack in the end portion, another dielectric elevationally between immediately vertically-adjacent control gate lines in the stack, the channels in individual of the NAND strings being interconnected; and
dummy structures extending vertically through the control gate lines and the another dielectric in the end portion.

2. The memory array of claim 1 further comprising contacts in the end portion.

3. The memory array of claim 1 wherein the dummy structures comprise at least some of the same material as that of the NAND strings.

4. The memory array of claim 3 wherein the dummy structures comprise a plurality of the same materials as that of the NAND strings.

5. The memory array of claim 4 wherein the same materials are arranged in the same lateral order relative one another in the NAND strings and n the dummy structures.

6. The memory array of claim 1 wherein the channels in the individual NAND strings comprise hollow cylinders.

7. The memory array of claim 1 wherein the channels in the individual NAND strings comprise laterally solid pillars.

8. The memory array of claim 1 wherein the control gate lines individually completely surround the dielectric material of the individual NAND strings.

9. The memory array of claim 1 wherein the control gate lines individually completely surround individual of the dummy structures.

10. A memory array comprising a stack of memory cells of NAND architecture:
a substrate comprising a primary portion and an end portion;
a plurality of NAND strings of vertically oriented transistors in the primary portion; the transistors individually comprising a channel comprising a hollow cylinder of semiconductive material, a tunnel dielectric laterally outward of the channel, a charge trapping material laterally outward of the tunnel dielectric, a dielectric material laterally outward of the charge trapping material, and a control gate laterally outward of the dielectric material; the control gate comprising a portion of one of a plurality of horizontally extending control gate lines, the control gate lines extending horizontally farther in the end portion moving deeper into the stack in the end portion, another dielectric elevationally between immediately vertically-adjacent control gate lines in the stack, the channels in individual of the NAND strings being interconnected by the hollow cylinder semiconductive material; and
dummy structures extending vertically through the control gate lines and the another dielectric in the end portion, the dummy structure comprising a hollow cylinder of semiconductive material of the same composition as the hollow cylinder semiconductive material of the channels.

11. The memory array of claim 10 further comprising contacts in the end portion.

12. The memory array of claim 10 wherein the control gate lines individually completely surround the dielectric material of the individual NAND strings.

13. The memory array of claim 10 wherein the control gate lines individually completely surround individual of the dummy structures.

14. A memory array comprising a stack of memory cells of NAND architecture:
a substrate comprising a primary portion and an end portion;
a plurality of NAND strings of vertically oriented transistors in the primary portion; the transistors individually comprising a channel, a tunnel dielectric laterally outward of the channel, a charge trapping material laterally outward of the tunnel dielectric, a dielectric material laterally outward of the charge trapping material, and a control gate laterally outward of the dielectric material; the control gate comprising a portion of one of a plurality of horizontally extending control gate lines, the control gate lines extending horizontally farther in the end portion moving deeper into the stack in the end portion, another dielectric elevationally between immediately vertically-adjacent control gate lines in the stack, the channels in individual of the NAND strings being interconnected;
dummy structures extending vertically through the control gate lines and the another dielectric in the end portion, the dummy structures individually comprising material of the same composition as that of the channels of the vertically oriented transistors;
material of the same composition as that of the tunnel dielectric of the vertically oriented transistors laterally outward of the channel composition material;
material of the same composition as that of the charge trapping material of the vertically oriented transistors laterally outward of the material of the same composition as that of the tunnel dielectric; and
material of the same composition as that of the control gate laterally outward of the material of the same composition as that of the charge trapping material.

15. The memory array of claim 14 wherein the control gate lines individually completely surround the dielectric material of the individual NAND strings.

16. The memory array of claim 14 wherein the control gate lines individually completely surround individual of the dummy structures.

17. A memory array comprising a stack of memory cells of NAND architecture:
a substrate comprising a primary portion and an end portion;
a plurality of NAND strings of vertically oriented transistors in the primary portion; the transistors individually comprising a channel, a tunnel dielectric laterally outward of the channel, a charge trapping material laterally outward of the tunnel dielectric, a dielectric material laterally outward of the charge trapping material, and a control gate laterally outward of the dielectric material; the control gate comprising a portion of one of a plurality of horizontally extending control gate lines, the control gate lines extending horizontally farther in the end portion moving deeper into the stack in the end portion, another dielectric elevationally between immediately vertically-adjacent control gate lines in the stack, the channels in individual of the NAND strings being interconnected;
dummy structures extending vertically through the control gate lines and the another dielectric in the end portion; and
a contact in the end portion between two immediately horizontally-adjacent of the dummy structures to individual of the control gate lines in the end portion.

18. The memory array of claim 17 wherein the control gate lines individually completely surround the dielectric material of the individual NAND strings.

19. The memory array of claim 17 wherein the control gate lines individually completely surround individual of the dummy structures.

Assignees

• Micron Technology Inc

Inventors

• Tang Sanh D
• Lindsay Roger W
• Parat Krishna K

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• G11C2213/75

  Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor · CPC title

• G11C2213/32

  Material having simple binary metal oxide structure · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title