Two material high K thermal encapsulant system

Patent metadata

Field	Value
Publication number	US-10475715-B2
Application number	US-201515037851-A
Country	US
Kind code	B2
Filing date	Jun 17, 2015
Priority date	Jun 17, 2015
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.

First claim

The invention claimed is:

1. An electronic package comprising:
a first die;
a second die stacked onto the first die; and
a first encapsulant positioned between the first die and the second die, the first encapsulant including a first material, the first encapsulant occupying a plurality of separate and non-contiguous volumes between the first die and the second die;
a second encapsulant positioned between the first die and the second die, the second encapsulant including a second material that surrounds each of the plurality of separate and non-contiguous volumes between the first die and the second die, wherein the first material has a higher thermal conductivity than the second material, and the second material provides greater adhesion between the first and second dies than the first material; and
a third encapsulant positioned between the first die and the second die, the third encapsulant including a third material, the third encapsulant occupies a separate and non-contiguous volume between the first die and the second die, wherein the third material has a different thermal conductivity than the first material and the second material.

2. The electronic package of claim 1 , wherein the first die and the second die are electrically connected through interconnects.

3. The electronic package of claim 2 , wherein the second encapsulant surrounds the interconnects.

4. The electronic package of claim 2 , wherein the interconnects extend around at least a portion of a periphery of one of the first die and the second die.

5. The electronic package of claim 1 , wherein a first filler in the first material is more densely packed than a second filler in the second material.

6. The electronic package of claim 5 , wherein the first material and the second material include the same resin.

7. The electronic package of claim 1 , wherein the first die is a different size than the second die.

8. The electronic package of claim 1 , wherein the third material includes the same resin as at least one of the first material and the second material.

9. A method comprising:
placing a first encapsulant that is made of a first material onto a first die such that the first material occupies a plurality of separate and non-contiguous volumes between the first die and the second die;
placing a second encapsulant that is made of a second material onto the first die such that the third material occupies a separate and non-contiguous volume between the first die and the second die;
placing a third encapsulant that is made of a third material onto the first die such that the third encapsulant surrounds each of the plurality of separate and non-contiguous volumes of the first encapsulant between the first die and the second die and surrounds separate and non-contiguous volume of the third encapsulant between the first die and the second die, wherein the first material has a higher thermal conductivity than the third material and the third material provides greater adhesion between the first and second dies than the first material, wherein the third material has a different thermal conductivity than the first encapsulant and the second encapsulant; and
stacking a second die onto the first die such the first encapsulant and the second encapsulant are between the first die and the second die.

10. The method of claim 9 , wherein placing a second encapsulant onto the first die includes surrounding interconnects that electrically connect the first die to the second die with the second encapsulant.

11. The method of claim 9 , wherein placing a second encapsulant onto the first die includes placing the second encapsulant around at least a portion of a periphery of one the first die and the second die.

Assignees

• Intel Corp

Inventors

• Mcmahan Venmathy
• Nagarajan Sivakumar
• Bozorg-Grayeli Elah
• Mallik Amrita
• Chu Kuang-Han
• Wang Liwei
• Ananthakrishnan Nisha
• Weinman Craig J
• Eitan Amram

Classifications

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W90/721

  of bump connectors · CPC title