Parallel test structure

Patent metadata

Field	Value
Publication number	US-10475677-B2
Application number	US-201715682704-A
Country	US
Kind code	B2
Filing date	Aug 22, 2017
Priority date	Aug 22, 2017
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

First claim

What is claimed is:

1. An apparatus for parallel testing of large numbers of devices on an integrated circuit chip, comprising:
a voltage source connected to, and providing a test voltage to, an integrated circuit containing devices under test by performing a time-dependent dielectric breakdown (TDDB) test on the devices under test;
a current measuring device that measures leakage current from the devices under test;
a decoder connected to the devices under test, the decoder selectively connecting each device under test to the current measuring device;
efuses, each of the efuses being connected to a different one of the devices under test, the efuses separately electrically disconnecting each of the devices under test from the voltage source upon failure of a corresponding device under test;
resistors, each of the resistors being connected to a different one of the efuses, the resistors providing a low resistance path to ground during stress conditions of the TDDB test; and
protection circuits connected between the efuses and ground, each protection circuit providing an electrical path to ground around the decoder upon failure of the device under test.

2. The apparatus according to claim 1 , wherein the decoder is located on the same integrated circuit chip as the devices under test.

3. The apparatus according to claim 1 , wherein the decoder sequentially selects each device under test to measure leakage current and the current measuring device measures leakage current for each device under test individually.

4. The apparatus according to claim 1 , wherein at least one of the efuses and the resistors are located on the same integrated circuit chip as the devices under test.

5. The apparatus according to claim 1 , further comprising:
pass transistors connected between the efuses and the current measuring device, wherein the decoder sequentially selects each device under test to measure leakage current by turning on each pass transistor, and wherein the resistors are arranged to force current to flow through the current measuring device when the pass transistors are turned on.

6. The apparatus according to claim 1 , the protection circuits further comprising electro-static discharge (ESD) diodes.

7. A circuit for parallel testing of large numbers of devices on an integrated circuit chip, comprising:
a voltage source;
a current measuring device;
devices under test connected to the voltage source;
pass transistors connected between each device under test and the current measuring device;
a decoder selectively providing a pass signal to each pass transistor, the decoder selecting a device for testing, wherein the decoder sequentially selects each device for testing by turning on each pass transistor to measure leakage current with the current measuring device;
efuses, each of the efuses being connected to a different one of the devices under test between a device under test and a corresponding pass transistor, the efuses breaking an electric circuit for the device under test from the voltage source upon failure of a corresponding device under test;
resistors, each of the resistors being connected to a different one of the efuses, the resistors providing a low resistance path to ground during stress conditions of a time-dependent dielectric breakdown (TDDB) test and forcing current to flow through the current measuring device when the pass transistors are turned on; and
protection circuits connected between the efuses and ground, each protection circuit electrically isolating the decoder from the device under test upon failure of the device under test.

8. The circuit according to claim 7 , wherein the decoder is located on the same integrated circuit chip as the devices under test.

9. The circuit according to claim 7 , wherein the decoder produces a signal to select each device under test individually.

10. The circuit according to claim 9 , wherein the decoder sequentially selects devices to measure leakage current and skips known failed devices.

11. The circuit according to claim 7 , wherein at least one of the efuses and the resistors are located on the same integrated circuit chip as the devices under test.

12. The circuit according to claim 7 , the current measuring device measuring leakage current from the devices under test.

13. The circuit according to claim 7 , the protection circuits further comprising electro-static discharge (ESD) diodes.

14. A method for parallel testing of large numbers of devices, the method comprising:
providing an electrical circuit having devices for testing;
providing a test voltage and applying the test voltage to the devices according to a time-dependent dielectric breakdown (TDDB) test on the devices;
providing a decoder having a signal sequentially selecting each one of the devices undergoing the TDDB test;
providing a current measuring device and individually measuring leakage current from the selected one of the devices;
responsive to TDDB failure of any one of the devices, breaking an electric circuit for the one of the devices from the test voltage using efuses arranged in the electrical circuit; and
responsive to TDDB failure of any one of the devices, electrically isolating the decoder from the one of the devices using protection circuits arranged in the electrical circuit.

15. The method according to claim 14 , wherein the test voltage for the TDDB test is greater than the maximum operating voltage of the decoder.

16. The method according to claim 14 , wherein the test voltage is one of the same voltage for different devices and different voltages for different devices.

17. The method according to claim 14 , wherein the decoder produces a signal that sequentially connects each one of the devices undergoing the TDDB test to the current measuring device.

18. The method according to claim 14 , wherein the decoder is located on the same integrated circuit chip as the devices.

19. The method according to claim 14 , further comprising:
providing pass transistors connected between the efuses and the current measuring device; and
providing resistors in the electrical circuit, each of the resistors being connected to a different one of the efuses, wherein the decoder sequentially selects devices to measure leakage current by turning on each pass transistor, and wherein the resistors are arranged to provide a low resistance path to ground during stress conditions of the TDDB test and to force current to flow through the current measuring device when the pass transistors are turned on,
at least one of the efuses and the resistors being located on the same integrated circuit chip as the devices.

Assignees

• Globalfoundries Inc

Inventors

• Shen Tian
• Kumar Anil
• Song Yuncheng
• Yeap Kong Boon
• Filippi Jr Ronald G
• Cao Linjun
• Choi Seungman
• Christiansen Cathryn J
• Justison Patrick R

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P72/0604 Primary

  Process monitoring, e.g. flow or thickness monitoring · CPC title

• G01R31/2879

  related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads · CPC title

• G01R31/2858

  Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection · CPC title