Shift register and driving method, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-10475362-B2
Application number	US-201715569216-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	Oct 31, 2016
Publication date	Nov 12, 2019
Grant date	Nov 12, 2019

Abstract

A shift register, a gate driving circuit, a display device and a driving method. The shift register includes: a driving unit, configured to supply a gate line signal to a corresponding pixel unit group; and a compensation circuit provided corresponding to the driving unit; where the compensation circuit is configured to compensate for one or more threshold voltage offsets of one or more transistors in the driving unit.

First claim

The invention claimed is:

1. A shift register, comprising:
a driving unit, configured to supply a gate line signal to a corresponding pixel unit group; and
a compensation circuit provided corresponding to the driving unit,
wherein the compensation circuit is configured to compensate for one or more threshold voltage offsets of one or more transistors in the driving unit;
the compensation circuit comprises a first compensation transistor and a second compensation transistor, the first compensation transistor being an N-type transistor and the second compensation transistor being a P-type transistor;
a gate electrode of the first compensation transistor is connected with a second compensation signal line and a first electrode of the first compensation transistor, and a second electrode of the first compensation transistor is connected with a pull-up node of the driving unit;
a gate electrode of the second compensation transistor is connected with the second compensation signal line and a first electrode of the second compensation transistor, and a second electrode of the second compensation transistor is connected with the pull-up node of the driving unit; and
the second compensation signal line is used for supplying a compensation voltage to the first electrode of the first compensation transistor or the first electrode of the second compensation transistor.

2. The shift register according to claim 1 , wherein the driving unit comprises:
a pull-up circuit, configured to output a first clock signal as the gate line signal;
a pull-up control circuit, configured to control a turning-on time of the pull-up circuit;
a pull-down circuit, configured to pull down the gate line signal to a low voltage level at a first time period;
a pull-down maintaining circuit, configured to maintain the low voltage level of the gate line signal; and
a pull-down maintaining control circuit, configured to maintain a pull-down control point at the low voltage level;
wherein the pull-up circuit or the pull-down maintaining control circuit comprises a transistor; and
the compensation circuit is configured to write a compensation voltage into part of transistors in the pull-up circuit or the pull-down maintaining control circuit.

3. The shift register according to claim 2 , wherein:
the pull-up control circuit comprises a first transistor, a first electrode of the first transistor is connected with an input signal line to receive an input signal, a gate electrode of the first transistor is connected with the first electrode of the first transistor, and a second electrode of the first transistor is connected with a pull-up node;
the pull-up circuit comprises a second transistor, a gate electrode of the second transistor is connected with the pull-up node, a first electrode of the second transistor is connected with a first clock terminal, and a second electrode of the second transistor is connected with an output terminal;
the pull-down circuit comprises a third transistor, a first electrode of the third transistor is connected with the output terminal, a gate electrode of the third transistor is connected with a reset signal line, a second electrode of the third transistor is connected with a first power line, the first power line is used for transmitting a first voltage, and the reset signal line is used for transmitting a reset signal;
the pull-down maintaining control circuit comprises a fourth transistor and a fifth transistor, a first electrode of the fourth transistor is connected with a second clock signal line, a gate electrode of the fourth transistor is connected with a second pull-down node, a second electrode of the fourth transistor is connected with a first pull-down node; a first electrode of the fifth transistor is connected with the first pull-down node, a gate electrode of the fifth transistor is connected with the pull-up node, a second electrode of the fifth transistor is connected with the first power line; the second clock signal line is used for transmitting a second clock signal; and
the pull-down maintaining circuit comprises a sixth transistor and a seventh transistor, first electrodes of both the sixth transistor and the seventh transistor are connected with the first power line, gate electrodes of both the sixth transistor and the seventh transistor are connected with the first pull-down node, and a second electrode of the sixth transistor is connected with the pull-up node and a second electrode of the seventh transistor is connected with the output terminal.

4. The shift register according to claim 3 , wherein:
the pull-down maintaining control circuit further comprises an eighth transistor and a ninth transistor;
a first electrode of the eighth transistor is connected with the second pull-down node, a gate electrode of the eighth transistor is connected with the pull-up node, and a second electrode of the eighth transistor is connected with the first power line; and
a first electrode of the ninth transistor is connected with the second clock signal line to receive the second clock signal, a gate electrode of the ninth transistor is connected with the first electrode of the ninth transistor, and a second electrode of the ninth transistor is connected with the second pull-down node.

5. The shift register according to claim 3 , further comprising a reset circuit, configured to make the pull-up node to discharge during an initialization phase.

6. The shift register according to claim 5 , wherein the reset circuit comprises a tenth transistor, a first electrode of the tenth transistor is connected with the pull-up node, a gate electrode of the tenth transistor is connected with a reset signal terminal, and a second electrode of the tenth transistor is connected with the first power line.

7. A gate driving circuit, comprising the shift register according to claim 1 .

8. A display device, comprising the gate driving circuit according to claim 7 and a display panel connected with the gate driving circuit.

9. A display device, comprising a gate driving circuit and a display panel connected with the gate driving circuit,
wherein the gate driving circuit comprises a shift register,
the shift register comprises:
a driving unit, configured to supply a gate line signal to a corresponding pixel unit group; and
a compensation circuit provided corresponding to the driving unit,
wherein the compensation circuit is configured to compensate for one or more threshold voltage offsets of one or more transistors in the driving unit,
the compensation circuit comprises:
a compensation transistor, a gate electrode of the compensation transistor being connected with a compensation control line, a first electrode of the compensation transistor being connected with a first compensation signal line, and a second electrode of the compensation transistor being connected with a pull-up node, and
the compensation control line is used for supplying a control signal to the gate electrode of the compensation transistor for controlling turning on of the compensation transistor; and the first compensation signal line is used for supplying a positive compensation voltage or a negative compensation voltage to the first electrode of the compensation transistor, and

the display device further comprises:
a timing and temperature-measuring device, configured to measure an operation time and an operation temperature of a respective driving unit of the gate driving circuit when the display panel is operating, to obtain a threshold voltage offset state of a transistor in a pull-up circuit or a pull-down maintaining control circuit of the respective driving unit based on the measured operation time and operation temperature, and to calculate a compensa

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Wang Zixuan

Classifications

• G09G2320/043

  Preventing or counteracting the effects of ageing · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2320/041

  Temperature compensation · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title