Gate driver circuit, gate driving method, gate-on-array circuit, display device, and electronic product

Patent metadata

Field	Value
Publication number	US-9620061-B2
Application number	US-201414415701-A
Country	US
Kind code	B2
Filing date	Apr 25, 2014
Priority date	Dec 30, 2013
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

The gate driver circuit is connected to a row of pixel units, each pixel unit includes a pixel driving module and a light-emitting device connected to each other, the pixel driving module including a driving transistor, a driving module and a compensating module, the compensating module being connected to a gate scanning signal, and the driving module being connected to a driving control signal and a driving voltage. The gate driver circuit includes a row pixel controlling unit configured to provide the gate scanning signal to the compensating module and provide the driving voltage to the driving module, so as to control the compensating module to compensate for a threshold voltage of the driving transistor; and a driving control unit configured to provide the driving control signal to the driving module so as to control the driving module to drive the light-emitting device.

First claim

What is claimed is:

1. A gate driver circuit, connected to a row of pixel units, each pixel unit includes a pixel driving module and a light-emitting device connected to each other, the pixel driving module including a driving transistor, a driving module and a compensating module, the compensating module being connected to a gate scanning signal, and the driving module being connected to a driving control signal and a driving voltage, the gate driver circuit comprising:
a row pixel controlling unit configured to provide the gate scanning signal to the compensating module and provide the driving voltage to the driving module, so as to control the compensating module to compensate for a threshold voltage of the driving transistor;
a driving control unit configured to provide the driving control signal to the driving module so as to control the driving module to drive the light-emitting device,
wherein the row pixel controlling unit comprises
a first start signal input end, a first control clock input end, a second control clock input end, a reset signal input end, an input clock end, a carry signal output end, a cut-off control signal output end, an output level end, an output level pull-down control end, a gate scanning signal output end,
a first pull-up node potential pull-up module configured to pull up a potential of a first pull-up node to a high level when a first control clock signal and a first start signal are at a high level,
a first storage capacitor connected between the first pull-up node and the carry signal output end,
a first pull-up node potential pull-down module configured to pull down the potential of the first pull-up module to a first low level when a potential of a first pull-down node or a second pull-down node is a high level,
a first control clock switch configured to enable the first control clock input end to be electrically connected to the first pull-down node when the first control clock signal is at a high level,
a second control clock switch configured to enable the second control clock input end to be electrically connected to the second pull-down node when a second control clock signal is at a high level,
a first pull-down node potential pull-down module configured to pull down the potential of the first pull-down node to the first low level when the potential of the first pull-up node or the second pull-down node is a high level, and
a second pull-down node potential pull-down module connected to the reset signal input end and configured to pull down the potential of the second pull-down node to the first low level when the potential of the first pull-up node or the first pull-down node is a high level,

a first carry control module configured to enable the carry signal output end to be electrically connected to the second control clock input end when the potential of the first pull-up node is a high level;
a first carry signal pull-down module configured to pull down a potential of a carry signal to the first low level when the potential of the first pull-down node or the second pull-down node is a high level;
a first cut-off control module configured to enable the second control clock input end to be electrically connected to the cut-off control signal output end when the potential of the first pull-up node is a high level, and enable the cut-off control signal output end to be electrically connected to a second low level output end when the potential of the first pull-down node or the second pull-down node is a high level;
a first feedback module configured to transmit a cut-off control signal to the first pull-up node potential pull-up module and the first pull-up node potential pull-down module when the carry signal is at a high level;
a gate scanning signal control module configured to enable the second control clock input end to be electrically connected to the gate scanning signal output end when the potential of the first pull-up node is a high level;
an input clock switch configured to enable the input clock end to be electrically connected to the output level pull-down control end when the potential of the first pull-up node is a high level;
a gate scanning signal pull-down module configured to pull down a potential of the gate scanning signal to a second low level when the potential of the first pull-down node or the second pull-down node is a high level;
an output level pull-down control module configured to pull down a potential of the output level pull-down control end to the second low level when the potential of the first pull-down node or the second pull-down node is a high level;
an output level pull-up module configured to pull up an output level to a high level when the output level pull-down control end outputs the second low level; and
an output level pull-down module configured to pull down the output level to the second low level when the output level pull-down control end outputs a high level.

2. The gate driver circuit according to claim 1 , wherein:
the driving control unit comprises a second start signal input end, a third control clock input end, a fourth control clock input end, a driving control signal output end, and a driving control signal pull-down control end;
the reset signal input end, the carry signal output end and the cut-off control signal output end are connected to the driving control unit; and
the driving control unit further comprises
a second pull-up node potential pull-up module configured to pull up a potential of a second pull-up node to a high level when a third control clock signal and a second start signal are at a high level,
a second storage capacitor connected between the second pull-up node and the carry signal output end,
a second pull-up node potential pull-down module configured to pull down the potential of the second pull-up node to the first low level when the potential of the first pull-down node or the second pull-down node is a high level,
a third control clock switch configured to enable the third control clock input end to be electrically connected to a third pull-down node when the third control clock signal is at a high level,
a fourth control clock switch configured to enable the fourth control clock input end to be electrically connected to a fourth pull-down node when a fourth control clock signal is at a high level,
a third pull-down node potential pull-down module configured to pull down a potential of the third pull-down node to the first low level when the potential of the second pull-up node or a potential of the fourth pull-down node is a high level,
a fourth pull-down node potential pull-down module connected to the reset signal input end and configured to pull down the potential of the fourth pull-down node to the first low level when the potential of the second pull-up node or the third pull-down node is a high level,
a second carry control module configured to enable the carry signal output end to be electrically connected to the fourth control clock input end when the potential of the second pull-up node is a high level,
a second carry signal pull-down module configured to pull down the potential of the carry signal to the first low level when the potential of the third pull-down node or the fourth pull-down node is a high level,
a second cut-off control module configured to enable the fourth control clock input end to be electrically connected to the cut-off control signal output end when the potential of the second pull-up node is a high level, and enable the cut-off control signal output end to be electrically connected to the second low level output end when the potential of the third pull-down node or the fourth pull-down node is a high level,
a second feedback module configured to transmit the cut-off control signal to the second pull-up node potential pull-up module and the second pull-up node potential pull-down module w

Assignees

• Boe Technology Group Co Ltd

Inventors

• Cao Kun
• Wu Zhongyuan
• Duan Liye

Classifications

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2320/043

  Preventing or counteracting the effects of ageing · CPC title

• G09G2310/0262

  The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title