Inductor and capacitor integrated on a substrate

Patent metadata

Field	Value
Publication number	US-10470309-B2
Application number	US-201514859320-A
Country	US
Kind code	B2
Filing date	Sep 20, 2015
Priority date	Sep 20, 2015
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

An integrated circuit device, such as a system-on-a-chip (SOC) device that includes an integrated or embedded voltage regulator, comprises an integrated capacitor and an integrated inductor having a magnetic core that can be fabricated in the same process as the capacitive structure of the integrated capacitor.

First claim

What is claimed is:

1. A device, comprising:
a substrate comprising first and second surfaces opposite each other and a plurality of vias through the substrate, the vias comprising a plurality of sidewalls in the substrate;
a third conductor on the first surface of the substrate;
a capacitor on the third conductor, the capacitor comprising:
a first conductive layer;
a second conductive layer; and
an insulator layer comprising a dielectric material between the first and second conductive layers; and

an inductor, comprising a magnetic core, the magnetic core comprising:
a first magnetic layer disposed on the first surface of the substrate; and
an insulator layer disposed over the first magnetic layer, the insulator layer of the inductor comprising the same dielectric material as the insulator layer of the capacitor,
wherein the capacitor and the magnetic core of the inductor are fabricated simultaneously; and

a first conductor comprising at least a first conductor portion disposed over but not in contact with the first magnetic layer and at least a second conductor portion extending over at least one of the sidewalls of at least one of the vias of the substrate.

2. The device of claim 1 , further comprising a conductive path between the capacitor and the inductor.

3. The device of claim 1 , wherein the inductor further comprises a second magnetic layer disposed over the insulator layer of the inductor.

4. The device of claim 3 , wherein the second magnetic layer of the inductor and the second conductive layer of the capacitor are fabricated in the same process.

5. The device of claim 3 , wherein the inductor further comprises an interlayer dielectric between the first conductor and the second magnetic layer.

6. The device of claim 5 , wherein the first conductor of the inductor comprises a plurality of first portions over the interlayer dielectric, a plurality of second portions over the sidewalls of at least some of the vias of the substrate, and a plurality of third portions under the second surface of the substrate, the pluralities of first, second and third portions of the first conductor forming a coil of the inductor.

7. The device of claim 1 , wherein the dielectric material of the insulator layer of the capacitor and the insulator layer of the inductor comprises silicon oxide (SiO 2 ).

8. The device of claim 1 , wherein the first conductor of the inductor comprises copper plating.

9. The device of claim 1 , wherein the capacitor further comprises:
a second conductor coupled to the first conductive layer, the second conductor comprising at least one portion extending over at least one of the sidewalls of at least one of the vias of the substrate; and
the third conductor coupled to the second conductive layer.

10. The device of claim 9 , wherein the second and third conductors of the capacitor comprise copper plating.

11. The device of claim 9 , wherein the capacitor further comprises an interlayer dielectric positioned to provide electrical insulation between the second and third conductors of the capacitor.

12. The device of claim 1 , wherein the substrate comprises at least one of a glass substrate, a silicon substrate, a ceramic substrate, and an organic substrate.

13. An integrated circuit device, comprising:
a substrate comprising first and second surfaces opposite each other and a plurality of vias through the substrate, the vias comprising a plurality of sidewalls in the substrate;
a third conductor on the first surface of the substrate; and
a passive circuit, comprising:
a capacitor on the third conductor, the capacitor comprising:
a first conductive layer;
a second conductive layer; and
an insulator layer comprising a dielectric material between the first and second conductive layers; and
an inductor, comprising a magnetic core, the magnetic core comprising:
a first magnetic layer disposed on the first surface of the substrate;
an insulator layer disposed on the first magnetic layer, the insulator layer of the inductor comprising the same dielectric material as the insulator layer of the capacitor,
wherein the capacitor and the magnetic core of the inductor are fabricated simultaneously; and

a first conductor comprising at least a first conductor portion disposed over but not in contact with the first magnetic layer and at least a second conductor portion extending over at least one of the sidewalls of at least one of the vias of the substrate.

14. The integrated circuit device of claim 13 , wherein the inductor further comprises a second magnetic layer disposed on the insulator layer of the inductor.

15. The integrated circuit device of claim 14 , wherein the inductor further comprises an interlayer dielectric between the first conductor and the second magnetic layer.

16. The integrated circuit device of claim 15 , wherein the first conductor of the inductor comprises a plurality of first portions over the interlayer dielectric, a plurality of second portions over the sidewalls of at least some of the vias of the substrate, and a plurality of third portions under the second surface of the substrate, the pluralities of first, second and third portions of the first conductor forming a coil of the inductor.

17. The integrated circuit device of claim 13 , wherein the capacitor further comprises:
a second conductor coupled to the first conductive layer, the second conductor comprising at least one portion extending over at least one of the sidewalls of at least one of the vias of the substrate;
the third conductor coupled to the second conductive layer; and
an interlayer dielectric positioned to provide electrical insulation between the second and third conductors of the capacitor.

18. The integrated circuit device of claim 13 , wherein the passive circuit comprises a circuit selecting from the group consisting of a voltage regulator, a power amplifier, a radio frequency circuit, and a wireless charging circuit.

Assignees

• Qualcomm Inc

Inventors

• Erturk Mete
• Mahmoudi Farsheed
• Doyle James Thomas
• Shenoy Ravindra Vaman
• Kim Jitae

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H05K3/426

  initial plating of through-holes in substrates without metal · CPC title

• H05K1/165

  incorporating printed inductors · CPC title