Processors and methods with configurable network-based dataflow operator circuits

Patent metadata

Field	Value
Publication number	US-10469397-B2
Application number	US-201715640540-A
Country	US
Kind code	B2
Filing date	Jul 1, 2017
Priority date	Jul 1, 2017
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

Systems, methods, and apparatuses relating to configurable network-based dataflow operator circuits are described. In one embodiment, a processor includes a spatial array of processing elements, and a packet switched communications network to route data within the spatial array between processing elements according to a dataflow graph to perform a first dataflow operation of the dataflow graph, wherein the packet switched communications network further comprises a plurality of network dataflow endpoint circuits to perform a second dataflow operation of the dataflow graph.

First claim

What is claimed is:

1. A processor comprising:
a spatial array of processing elements; and
a packet switched communications network to route data within the spatial array between processing elements according to a dataflow graph to perform a first dataflow operation of the dataflow graph, wherein the packet switched communications network further comprises a plurality of network dataflow endpoint circuits to perform a second dataflow operation of the dataflow graph.

2. The processor of claim 1 , wherein a network dataflow endpoint circuit of the plurality of network dataflow endpoint circuits comprises:
a network ingress buffer to receive input data from the packet switched communications network; and
a spatial array egress buffer to output resultant data to the spatial array of processing elements according to the second dataflow operation on the input data.

3. The processor of claim 2 , wherein the spatial array egress buffer is to output the resultant data based on a scheduler within the network dataflow endpoint circuit monitoring the packet switched communications network.

4. The processor of claim 3 , wherein the spatial array egress buffer is to output the resultant data based on the scheduler within the network dataflow endpoint circuit monitoring a selected channel of multiple network virtual channels of the packet switched communications network.

5. The processor of claim 1 , wherein a network dataflow endpoint circuit of the plurality of network dataflow endpoint circuits comprises a spatial array ingress buffer to receive control data from the spatial array that causes a network ingress buffer of the network dataflow endpoint circuit that received input data from the packet switched communications network to output resultant data to the spatial array of processing elements according to the second dataflow operation on the input data and the control data.

6. The processor of claim 1 , wherein a network dataflow endpoint circuit of the plurality of network dataflow endpoint circuits is to stall an output of resultant data of the second dataflow operation from a spatial array egress buffer of the network dataflow endpoint circuit when a backpressure signal from a downstream processing element of the spatial array of processing elements indicates that storage in the downstream processing element is not available for the output of the network dataflow endpoint circuit.

7. The processor of claim 1 , wherein a network dataflow endpoint circuit of the plurality of network dataflow endpoint circuits is to send a backpressure signal to stall a source from sending input data on the packet switched communications network into a network ingress buffer of the network dataflow endpoint circuit when the network ingress buffer is not available.

8. The processor of claim 1 , wherein the spatial array of processing elements comprises:
a plurality of processing elements; and
an interconnect network between the plurality of processing elements to receive an input of the dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network, the plurality of processing elements, and the plurality of network dataflow endpoint circuits with each node represented as a dataflow operator in either of the plurality of processing elements and the plurality of network dataflow endpoint circuits, and the plurality of processing elements and the plurality of network dataflow endpoint circuits are to perform an operation by an incoming operand set arriving at each of the dataflow operators of the plurality of processing elements and the plurality of network dataflow endpoint circuits.

9. The processor of claim 1 , wherein the spatial array of processing elements comprises a circuit switched network to transport the data within the spatial array between processing elements according to the dataflow graph.

10. A method comprising:
routing, with a packet switched communications network, data within a spatial array of processing elements between the processing elements according to a dataflow graph;
performing a first dataflow operation of the dataflow graph with the processing elements; and
performing a second dataflow operation of the dataflow graph with a plurality of network dataflow endpoint circuits of the packet switched communications network.

11. The method of claim 10 , wherein the performing the second dataflow operation comprises:
receiving input data from the packet switched communications network with a network ingress buffer of a network dataflow endpoint circuit of the plurality of network dataflow endpoint circuits; and
outputting resultant data from a spatial array egress buffer of the network dataflow endpoint circuit to the spatial array of processing elements according to the second dataflow operation on the input data.

12. The method of claim 11 , wherein the outputting comprises outputting the resultant data based on a scheduler within the network dataflow endpoint circuit monitoring the packet switched communications network.

13. The method of claim 12 , wherein the outputting comprises outputting the resultant data based on the scheduler within the network dataflow endpoint circuit monitoring a selected channel of multiple network virtual channels of the packet switched communications network.

14. The method of claim 10 , wherein the performing the second dataflow operation comprises:
receiving control data, with a spatial array ingress buffer of a network dataflow endpoint circuit of the plurality of network dataflow endpoint circuits, from the spatial array; and
configuring the network dataflow endpoint circuit to cause a network ingress buffer of the network dataflow endpoint circuit that received input data from the packet switched communications network to output resultant data to the spatial array of processing elements according to the second dataflow operation on the input data and the control data.

15. The method of claim 10 , wherein the performing the second dataflow operation comprises:
stalling an output of the second dataflow operation from a spatial array egress buffer of a network dataflow endpoint circuit of the plurality of network dataflow endpoint circuits when a backpressure signal from a downstream processing element of the spatial array of processing elements indicates that storage in the downstream processing element is not available for the output of the network dataflow endpoint circuit.

16. The method of claim 10 , wherein the performing the second dataflow operation comprises:
sending a backpressure signal from a network dataflow endpoint circuit of the plurality of network dataflow endpoint circuits to stall a source from sending input data on the packet switched communications network into a network ingress buffer of the network dataflow endpoint circuit when the network ingress buffer is not available.

17. The method of claim 10 , wherein the routing, performing the first dataflow operation, and performing the second dataflow operation comprises:
receiving an input of a dataflow graph comprising a plurality of nodes;
overlaying the dataflow graph into the spatial array of processing elements and the plurality of network dataflow endpoint circuits with each node represented as a dataflow operator in either of the processing elements and the plurality of network dataflow endpoint circuits; and
performing the first dataflow operation with the processing elements and performing the second dataflow operation with the plurality of network dataflow endpoint circuits when an incoming operan

Assignees

• Intel Corp

Inventors

• Fleming Kermin
• Glossop Kent D
• Steely Jr Simon C

Classifications

• H04L45/72

  Routing based on the source address · CPC title

• H04L49/3027

  Output queuing · CPC title

• H04L49/254

  Centralised controller, i.e. arbitration or scheduling · CPC title

• H04L47/62 Primary

  characterised by scheduling criteria · CPC title

• H04L49/3018 Primary

  Input queuing · CPC title