Successive approximation register analog-to-digital converter, electronic device and method therefor

Patent metadata

Field	Value
Publication number	US-10469095-B2
Application number	US-201816119117-A
Country	US
Kind code	B2
Filing date	Aug 31, 2018
Priority date	Nov 14, 2017
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A successive approximation register, SAR, analog-to-digital converter, ADC, ( 400 ) is described. The SAR ADC ( 400 ) includes: an analog input signal ( 410 ); an ADC core ( 414 ) configured to receive the analog input signal ( 410 ) and comprising: a digital to analog converter, DAC ( 430 ) located in a feedback path; and a SAR controller ( 418 ) configured to control an operation of the DAC ( 430 ), wherein the DAC ( 430 ) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller ( 418 ) to an analog form; a digital signal reconstruction circuit ( 450 ) configured to convert the digital codes from the SAR controller ( 418 ) to a binary form; and an output coupled to the digital signal reconstruction circuit ( 450 ) and configured to provide a digital data output ( 460 ). The DAC ( 430 ) is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and the SAR controller ( 418 ) is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC ( 430 ) and the digital signal reconstruction circuit ( 450 ) to implement a small signal mapping mode of operation.

First claim

The invention claimed is:

1. A radar unit having a successive approximation register, SAR, analog-to-digital converter, ADC, comprises:
an analog input signal;
an ADC core configured to receive the analog input signal and comprising:
a digital to analog converter, DAC located in a feedback path; and
a SAR controller configured to control an operation of the DAC, wherein the DAC comprises a number of DAC cells, arranged to convert a digital code from the SAR controller to an analog form;

a digital signal reconstruction circuit configured to convert the digital codes from the SAR controller to a binary form;
an output coupled to the digital signal reconstruction circuit and configured to provide a digital data output;
wherein the SAR ADC is characterised by:
wherein the DAC is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and
the SAR controller is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC and the digital signal reconstruction circuit to operate in the small signal mapping mode of operation, the small signal mapping mode of operation being used for at least one of noise reduction and background calibration for the radar unit.

2. The radar unit having the SAR ADC of claim 1 wherein the SAR controller is configured to determine whether the analog input signal is a small signal within a particular range in response to observing an initial plurality of decisions output from the comparator to determine a signal strength of the sampled analog input signal.

3. The radar unit having the SAR ADC of claim 1 wherein the SAR ADC is configured to operate in a time multiplexed manner and the SAR controller is configured to analyse a first chirp in one chirp sequence of a received signal in order to detect a signal strength of the sampled analog input signal and to use this information for converting subsequent chirps.

4. The radar unit having the SAR ADC of claim 1 further comprising an auxiliary signal level detection path that comprises a signal level range detector circuit coupled to a multiplexer and the SAR controller and arranged to determine a signal strength of the sampled analog input signal, and in response thereto inform the SAR controller and the digital signal reconstruction circuit.

5. The radar unit having the SAR ADC of claim 4 wherein the SAR controller is configured to adaptively set one or more threshold(s) applied by the signal level range detector circuit to influence when the small signal mapping mode of operation is adopted by the DAC and the digital signal reconstruction circuit.

6. The radar unit having the SAR ADC of claim 1 wherein the ADC core comprises:
a multiplexer configured to receive the analog input signal;
a track and hold (T/H) circuit coupled to an output of the multiplexer and configured to periodically sample the analog input signal; and
a comparator circuit coupled to the T/H circuit and configured to receive a difference of the sampled analog input signal and the DAC output signal (V sampled −V DAC ), and compare the difference with one or more threshold levels.

7. The radar unit having the SAR ADC of claim 6 wherein the SAR controller ( 418 ) is configured to determine whether the analog input signal is a small signal within a particular range in response to identifying that the output from the comparator ( 416 ) exhibits a code pattern for the initial plurality of decisions within a conversion phase of operation of the SAR ADC.

8. The radar unit having the SAR ADC of claim 1 wherein in response to the SAR controller identifying that the received analog signal is a small signal level, the SAR controller configures the DAC to skip a portion of a conversion operation of the sampled analog signal.

9. The radar unit having the SAR ADC of claim 8 wherein the SAR controller configures the DAC to skip a plurality of most significant bit, MSB, DAC cells of the conversion operation in response to a detection of a small received signal level.

10. The radar unit having the SAR ADC of claim 9 wherein the plurality of DAC cells that are skipped comprises the corresponding DAC cells being placed in a balanced or hold mode of a tri-state DAC switching scheme, and whereby corresponding weights stored in a digital domain are not used for output signal reconstruction by the digital signal reconstruction circuit.

11. The radar unit having the SAR ADC of claim 9 wherein the plurality of MSB DAC cells that are skipped occurs when the sampled analog input signal level is below a pre-set threshold level.

12. The radar unit having the SAR ADC of claim 1 wherein the DAC is configured to operate in a switched bit-wise mode of operation such that a digital representation of the analog input signal is provided to the SAR ADC output.

13. A radar unit comprises a baseband circuit having a successive approximation register, SAR, analog-to-digital converter, ADC, that comprises:
an analog input signal;
an ADC core configured to receive the analog input signal and comprising:
a digital to analog converter, DAC located in a feedback path; and
a SAR controller configured to control an operation of the DAC, wherein the DAC comprises a number of DAC cells, arranged to convert a digital code from the SAR controller to an analog form;

a digital signal reconstruction circuit configured to convert the digital codes from the SAR controller to a binary form;
an output coupled to the digital signal reconstruction circuit and configured to provide a digital data output;
wherein:
the DAC is configurable to support at least two mapping modes, including a small signal mapping mode of operation; and
the SAR controller is configured to identify when the received analog signal is a small signal level, and in response thereto re-configure the DAC and the digital signal reconstruction circuit to operate in the small signal mapping mode of operation, the small signal mapping mode of operation being used for at least one of noise reduction and background calibration for the radar unit.

14. The radar unit of claim 13 wherein the electronic device is a radar unit comprising at least one antenna coupled to at least one radio frequency circuit configured to receive and down-convert received radar signals, wherein the radar unit comprises a baseband circuit having the SAR ADC.

15. A method for digitizing a received analog signal to an output digital form in a successive approximation register, SAR, analog-to-digital converter, ADC, of a radar unit wherein the method comprises:
receiving and sampling an analog input signal;
controlling, by an SAR controller, an operation of a digital to analog converter, DAC, located in a feedback path of the SAR ADC and comprising a number of DAC cells;
converting by the DAC a digital code from the SAR controller to an analog form (V sampled −V DAC );
receiving a difference of the sampled analog input signal and the analog form of the digital code;
providing a digital data output by a digital signal reconstruction circuit
wherein the method is characterised by:
supporting at least two mapping modes by the DAC, including a small signal mapping mode of operation; and
identifying when the received analog input signal is a small signal level, and in response thereto re-configuring the DAC and the digital signal reconstruction circuit to operate in the small signal mapping mode of operation, the small signal mapping mode of operation being used for at least one of noise reduction and background calibration for the radar unit.

Assignees

• Nxp Bv

Inventors

• Lin Yu
• Janssen Erwin
• Dyachenko Vladislav

Classifications

• H03M1/187

  using an auxiliary analogue/digital converter · CPC title

• H03M1/1028

  at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/38 Primary

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/1004

  without interrupting normal operation, e.g. by providing an additional component for temporarily replacing components to be tested or calibrated (H03M1/1009, H03M1/1071 take precedence) · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title