Error measurement and calibration of analog to digital converters

Patent metadata

Field	Value
Publication number	US-9362938-B2
Application number	US-201414487166-A
Country	US
Kind code	B2
Filing date	Sep 16, 2014
Priority date	Sep 16, 2014
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

Methods of measuring capacitance error in a successive approximation register (SAR) analog to digital converter (ADC) are described, including a method in which said ADC includes a register and a digital to analog converter (DAC), and the method comprises connecting a first capacitance associated with a first bit of the DAC between a first reference voltage and a second reference voltage, connecting a first set of one or more capacitances associated with one or more other bits of the DAC between the first reference voltage and a third reference voltage, connecting the first capacitance between a first node and the third reference voltage, connecting the first set of one or more capacitances between the first node and the second reference voltage, and measuring a voltage at the first node to determine a representation of a difference between the first capacitance and a total capacitance of the first set of one or more capacitances.

First claim

What is claimed is:

1. A method of measuring capacitance error in a successive approximation register (SAR) analog to digital converter (ADC), said ADC including a register and a digital to analog converter (DAC), the method comprising:
connecting a first capacitance associated with a first bit of the DAC between a first reference voltage and a second reference voltage;
connecting a first set of one or more capacitances associated with one or more other bits of the DAC between the first reference voltage and a third reference voltage;
connecting the first capacitance between a first node and the third reference voltage;
connecting the first set of one or more capacitances between the first node and the second reference voltage; and
measuring a voltage at the first node to determine a representation of a difference between the first capacitance and a total capacitance of the first set of one or more capacitances;
the first reference voltage being a common mode voltage, the second reference voltage being one of a predetermined reference voltage and ground, and the third reference voltage being the other of the predetermined reference voltage and ground.

2. The method of claim 1 , wherein the one or more bits associated with the first set of one or more capacitances are less significant than the first bit.

3. The method of claim 1 , comprising connecting capacitances of the DAC associated with bits other than the first bit and the one or more other bits between the first reference voltage and one of the second and third reference voltages when the first capacitance is connected between the first reference voltage and the second reference voltage, and between the first node and the one of the second and third reference voltages when the first capacitance is connected between the first node and the third reference voltage.

4. The method of claim 1 , wherein measuring the voltage at the first node comprises connecting the first node to a first input of a comparator of the ADC, and operating the ADC to measure the voltage at the first node.

5. The method of claim 1 , wherein the first node is connected to a first input of a comparator of the ADC, and measuring the voltage at the first node comprises operating the ADC to measure the voltage at the first node.

6. The method of claim 1 , wherein the DAC is a differential DAC, and the method further comprises:
connecting a second capacitance associated with the first bit of the DAC between the first reference voltage and the second reference voltage;
connecting a second set of one or more capacitances associated with one or more other bits of the DAC between the first reference voltage and the third reference voltage;
connecting the second capacitance between a second node and the third reference voltage;
connecting the second set of one or more capacitances between the second node and the second reference voltage; and
measuring a voltage at the second node to determine a representation of an error between the second capacitance and a total capacitance of the second set of one or more capacitances.

7. The method of claim 6 , wherein at least one of the first node and the second node is connected to a respective input of a comparator of the DAC.

8. The method of claim 1 , further comprising:
connecting a further capacitance associated with a second bit of the DAC between the first reference voltage and the second reference voltage;
connecting a further set of one or more capacitances associated with one or more other bits of the DAC between the first reference voltage and a third reference voltage;
connecting the further capacitance between the first node and the third reference voltage;
connecting the further set of one or more capacitances between the first node and the second reference voltage; and
measuring a voltage at the first node to determine a further representation of a difference between the further capacitance and a total capacitance of the further set of one or more capacitances.

9. The method of claim 8 , further comprising determining a mismatch error of the further capacitance based on the first representation and the further representation.

10. The method of claim 1 , further comprising determining a mismatch error of the first capacitance based on the first representation.

11. The method of claim 1 , further comprising using the representation to correct an error in an output of the ADC.

12. The method of claim 1 , further comprising:
connecting the first capacitance and the first set of one or more capacitances between the first node and the second or third reference voltage;
connecting the first node to the first reference voltage;
providing a voltage at the first node to a first input of a comparator of the ADC;
providing the first reference voltage to a second input of the ADC; and
using the ADC to measure an offset voltage of the ADC.

13. The method of claim 12 , further comprising determining a mismatch error of the first capacitance based on the first representation and the offset voltage.

14. The method of claim 1 , comprising carrying out the method for a plurality of bits including the first bit.

15. The method of claim 14 , wherein the method is not carried out for one or more least significant bits (LSBs) of the DAC.

16. A successive approximation register (SAR) analog to digital converter (ADC) comprising:
a register; and
a digital to analog converter (DAC), the DAC comprising a plurality of switches and a plurality of capacitors, each of the plurality of capacitors having a capacitance;
wherein the DAC is configured to control the plurality of switches to:
connect a first capacitance associated with a first bit of the DAC between a first reference voltage and a second reference voltage;
connect a first set of one or more capacitances associated with one or more other bits of the DAC between the first reference voltage and a third reference voltage;
connect the first capacitance between a first node and the third reference voltage;
connect the first set of one or more capacitances between the first node and the second reference voltage; and

wherein the DAC is further configured to measure a voltage at the first node to determine a representation of a difference between the first capacitance and a total capacitance of the first set of one or more capacitances;
the first reference voltage being a common mode voltage, the second reference voltage being one of a predetermined reference voltage and ground, and the third reference voltage being the other of the predetermined reference voltage and ground.

17. A device comprising:
a successive approximation register (SAR) analog to digital converter (ADC), wherein the SAR ADC comprises
a register; and
a digital to analog converter (DAC), the DAC comprising a plurality of switches and a plurality of capacitors, each of the plurality of capacitors having a capacitance;
wherein the DAC is configured to control the plurality of switches to:
connect a first capacitance associated with a first bit of the DAC between a first reference voltage and a second reference voltage;
connect a first set of one or more capacitances associated with one or more other bits of the DAC between the first reference voltage and a third reference voltage;
connect the first capacitance between a first node and the third reference voltage;
connect the first set of one or more capacitances between the first node and the second reference voltage; and

wherein the DAC is further configured to measure a voltage at the first node to determine a rep

Assignees

• Qualcomm Technologies Int Ltd

Inventors

• Zare-Hoseini Hashem
• Mavridis Dimitrios

Classifications

• H03M1/1009

  Calibration · CPC title

• H03M1/466

  using switched capacitors · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/403

  using switched capacitors · CPC title

• H03M1/1071 Primary

  Measuring or testing · CPC title