Breakdown-based physical unclonable function

Patent metadata

Field	Value
Publication number	US-10469083-B2
Application number	US-201715644614-A
Country	US
Kind code	B2
Filing date	Jul 7, 2017
Priority date	Jul 10, 2016
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.

First claim

What is claimed is:

1. A method of implementing a physically unclonable function, the method comprising:
providing a device comprising at least one electronic structure, each electronic structure comprising a dielectric,
generating an electrical breakdown of the dielectric such that a conductive path is formed, in each of the at least one electronic structure, through the dielectric at a random position,
determining, for each of the at least one electronic structure, a distinct value of a set comprising at least two predetermined values, wherein the distinct value is determined by the position of the conductive path through the dielectric of the electronic structure.

2. The method of claim 1 , wherein the device comprises an array of transistors, and wherein generating the electrical breakdown comprises applying a high gate bias on each transistor to form a conductive path between a gate and randomly either a source or a drain of the transistor.

3. The method of claim 1 , further comprising generating plasma damage in the at least one electronic structure.

4. A PUF device for implementing a physically unclonable function, the device comprising:
at least one electronic structure, each electronic structure comprising a dielectric; and
a conductive path through the dielectric at a random position,
wherein each electronic structure is configured to output a distinct value of a set comprising at least two predetermined values, and wherein the distinct value is determined by the position of the conductive path through the dielectric.

5. The PUF device of claim 4 , wherein the conductive path is formed due to an electrical breakdown of the dielectric.

6. The PUF device of claim 4 , wherein the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at the random position.

7. The PUF device of claim 4 , wherein the at least one electronic structure comprises at least one circuit element that comprises a first terminal, a second terminal and a third terminal electrically insulated from each other by the dielectric.

8. The PUF device of claim 7 , wherein the at least one electronic structure is adapted for determining the distinct value by detecting the position as being either closer to the first terminal or closer to the second terminal.

9. The PUF device of claim 7 , wherein the at least one circuit element comprises a field effect transistor comprising a gate dielectric, a drain, a source and a gate terminal,
wherein the conductive path is either formed in the at least one electronic structure through the gate dielectric or the at least one electronic structure is adapted for generating the electrical breakdown in the gate dielectric such that the conductive path is formed through the gate dielectric, such that the conductive path conductively connects the gate terminal to at least one of the source and the drain, and
wherein the position is a position between the source and the drain.

10. The PUF device of claim 9 , wherein the at least one electronic structure is adapted for obtaining a voltage drop at the drain and at the source, and determining the distinct value as a function of the voltage drops.

11. The PUF device of claim 9 , wherein the conductive path is formed due to an electrical breakdown of the dielectric.

12. The PUF device of claim 11 , wherein the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at the random position.

13. The PUF device of claim 12 , wherein the device comprises an array of transistors, and wherein generating the electrical breakdown comprises applying a high gate bias on each transistor to form a conductive path between a gate and randomly either a source or a drain of the transistor.

14. The PUF device of claim 7 , wherein the at least one electronic structure comprises at least a further circuit element that comprises at least a first terminal, a second terminal and a third terminal electrically insulated from each other by the dielectric, the third terminal of the circuit element being connected to the third terminal of the further circuit element.

15. The PUF device of claim 14 , wherein the device is adapted for detecting a transistor breakdown in each of the circuit element and the further circuit element of the electronic structure.

16. The PUF device of claim 7 , further comprising a compliance-limited transistor switch in series with the at least one circuit element.

17. The PUF device of claim 4 , wherein the electrical breakdown is a soft breakdown.

18. The PUF device of claim 4 , further comprising a plurality of the electronic structures organized in an array, and further comprising a readout system for addressing an individual electronic structure, or a subset of the electronic structures, as function of row and/or column addresses and outputting the distinct value of the addressed electronic structure or the addressed subset of electronic structures.

19. The PUF device of claim 18 , wherein the readout system comprises a row multiplexer and/or a column multiplexer, and wherein the readout system comprises at least one comparator for comparing a pair of voltage differences sensed at a corresponding pair of different regions of the dielectric in the addressed electronic structure.

20. The PUF device of claim 18 , further comprising a plurality of arrays in a semiconductor die, each array of the arrays comprising a plurality of the electronic structures, each array being adapted for storing a corresponding encryption key.

Assignees

• Imec Vzw
• Univ Leuven Kath

Inventors

• Bury Erik
• Franco Jacopo
• Hellings Geert
• Degraeve Robin
• Kaczer Benjamin

Classifications

• H10P95/80

  Electrical treatments, e.g. for electroforming · CPC title

• H10W42/40

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H03K19/003 Primary

  Modifications for increasing the reliability {for protection} · CPC title

• H04L9/0861

  Generation of secret information including derivation or calculation of cryptographic keys or passwords · CPC title