Power converter

US10469064B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10469064-B2
Application numberUS-201816016896-A
CountryUS
Kind codeB2
Filing dateJun 25, 2018
Priority dateAug 7, 2017
Publication dateNov 5, 2019
Grant dateNov 5, 2019

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A signal converter circuit includes a frequency detection circuit configured to determine whether an external control signal is a PWM signal. A PWM frequency converter circuit is configured to detect, when a PWM signal is input, a duty cycle of the PWM signal and to generate a first digital signal. An AD converter is configured to generate a second digital signal based on an input DC voltage or a voltage attributable to a variable resistor to digital data using a maximum AD convertible input voltage as a duty cycle of 100%. An output signal generation circuit is configured to generate, based on the first or second digital signals output from the PWM frequency converter circuit or the AD converter, a PWM signal with a duty cycle based on that first or second digital signals.

First claim

Opening claim text (preview).

What is claimed is: 1. A power converter comprising: a signal converter circuit configured to receive an external control signal which is one of a pulse width modulation signal and a direct-current voltage, and to adjust a threshold used by a feedback circuit to detect an output voltage or electric current to be supplied to a load, wherein the signal converter circuit includes a frequency detection circuit configured to determine whether the external control signal is the pulse width modulation signal, a pulse width modulation frequency converter circuit configured to detect a duty cycle of the pulse width modulation signal and to generate a first digital signal based on the detected duty cycle, an analog-to-digital converter configured to generate a second digital signal based on a ratio of the direct-current voltage to a maximum analog-to-digital convertible input voltage, a multiplexer configured to select the first digital signal when the frequency detection circuit determines that the external control signal is the pulse width modulation signal, and to select the second digital signal when the frequency detection circuit determines that the external control signal is not the pulse width modulation signal, and an output signal generation circuit configured to generate as an output signal a first output pulse width modulation signal with a first duty cycle based on the first digital signal when the first digital signal is selected by the multiplexer and to generate as the output signal a second output pulse width modulation signal- with a second duty cycle based on the second digital signal when the second digital signal is selected by the multiplexer, and to supply the output signal to the feedback circuit, such that the output signal has the first duty cycle when the external control signal is the pulse width modulation signal, and has the second duty cycle when the external control signal is the direct current voltage. 2. A power converter comprising: a signal converter circuit configured to receive an external control signal which is one of a pulse width modulation signal and a direct-current voltage, and to adjust a threshold used by a feedback circuit to detect an output voltage or electric current to be supplied to a load, wherein the signal converter circuit includes a frequency detection circuit configured to determine whether the external control signal is the pulse width modulation signal, the frequency detection circuit binarizing the external control signal and determining that the external control signal is in the form of the pulse width modulation signal when the binarized signal has a frequency higher than a predetermined frequency, a pulse width modulation frequency converter circuit configured to detect a duty cycle of the pulse width modulation signal and to generate a first digital signal based on the detected duty cycle, an analog-to-digital converter configured to generate a second digital signal based on a ratio of the direct-current voltage to a maximum analog-to-digital convertible input voltage, a multiplexer configured to select the first digital signal when the frequency detection circuit determines that the external control signal is the pulse width modulation signal, and to select the second digital signal when the frequency detection circuit determines that the external control signal is not the pulse width modulation signal, and an output signal generation circuit configured to generate as an output signal a first output pulse width modulation signal with a first duty cycle based on the first digital signal when the first digital signal is selected by the multiplexer and to generate as the output signal a second output pulse width modulation signal- with a second duty cycle based on the second digital signal when the second digital signal is selected by the multiplexer, and to supply the output signal to the feedback circuit. 3. A power converter comprising: a signal converter circuit configured to receive an external control signal which is one of a pulse width modulation signal and a direct-current voltage, and to adjust a threshold used by a feedback circuit to detect an output voltage or electric current to be supplied to a load, wherein the signal converter circuit includes a frequency detection circuit configured to determine whether the external control signal is the pulse width modulation signal, a pulse width modulation frequency converter circuit configured to detect a duty cycle of the pulse width modulation signal and to generate a first digital signal based on the detected duty cycle, an analog-to-digital converter configured to generate a second digital signal based on a ratio of the direct-current voltage to a maximum analog-to-digital convertible input voltage, a multiplexer configured to select the first digital signal when the frequency detection circuit determines that the external control signal is the pulse width modulation signal, and to select the second digital signal when the frequency detection circuit determines that the external control signal is not the pulse width modulation signal, and an output signal generation circuit configured to generate as an output signal a first output pulse width modulation signal with a first duty cycle based on the first digital signal when the first digital signal is selected by the multiplexer and to generate as the output signal a second output pulse width modulation signal- with a second duty cycle based on the second digital signal when the second digital signal is selected by the multiplexer, and to supply the output signal to the feedback circuit the frequency detection circuit including a hysteresis comparator configured to binarize the external control signal, a flip-flop configured to be set by an output signal of the hysteresis comparator and reset by a signal obtained by delaying a reset signal with a predetermined frequency, a frequency division circuit configured to divide a frequency of an output signal of the flip-flop, to be reset by a logical AND signal indicating a logical AND between the reset signal and an inverted output signal of the flip-flop, and to output a determination signal indicating that the external control signal is the pulse width modulation signal when the output signal of the flip-flop is counted a predetermined number of times without being reset, and an AND circuit configured to inhibit, when the frequency division circuit outputs the determination signal, an input of the output signal of the flip-flop and to maintain the output of the determination signal. 4. A power converter comprising: a signal converter circuit configured to receive an external control signal which is one of a pulse width modulation signal and a direct-current voltage, and to adjust a threshold used by a feedback circuit to detect an output voltage or electric current to be supplied to a load, wherein the signal converter circuit includes a frequency detection circuit configured to determine whether the external control signal is the pulse width modulation signal, a pulse width modulation frequency converter circuit configured to detect a duty cycle of the pulse width modulation signal and to generate a first digital signal based on the detected duty cycle, an analog-to-digital converter configured to generate a second digital signal based on a ratio of the direct-current voltage to a maximum analog-to-digital convertible input voltage, a multiplexer configured to select the first digital signal when the frequency detection circuit determines that the external control signal is the pulse width modulation signal, and to select the second digital signal when the frequency detection circuit determines that the external control signal is not the pulse width modulation signal, and an output signal generation ci

Assignees

Inventors

Classifications

  • Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00) · CPC title

  • with digital control · CPC title

  • G06F3/05Primary

    Digital input using the sampling of an analogue quantity at regular intervals of time {, input from a/d converter or output to d/a converter} · CPC title

  • using analogue/digital converters of the type with conversion of voltage or current into frequency and measuring of this frequency · CPC title

  • H03K7/08Primary

    Duration or width modulation {; Duty cycle modulation} · CPC title

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Frequently asked questions

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What does patent US10469064B2 cover?
A signal converter circuit includes a frequency detection circuit configured to determine whether an external control signal is a PWM signal. A PWM frequency converter circuit is configured to detect, when a PWM signal is input, a duty cycle of the PWM signal and to generate a first digital signal. An AD converter is configured to generate a second digital signal based on an input DC voltage or…
Who is the assignee on this patent?
Fuji Electric Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/05. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 05 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).