Code modulator for code-modulating power with modulation code, code demodulator for code-demodulating code-modulated power with demodulation code, and controller thereof

Patent metadata

Field	Value
Publication number	US-10468960-B2
Application number	US-201715485712-A
Country	US
Kind code	B2
Filing date	Apr 12, 2017
Priority date	Sep 29, 2015
Publication date	Nov 5, 2019
Grant date	Nov 5, 2019

Abstract

A code modulator includes: a code-modulation circuit that code-modulates input power with a modulation code to generate code-modulated power which is alternating-current power; and a terminal through which the code-modulated power is transmitted, the terminal being connected to a transmission path.

First claim

What is claimed is:

1. A code modulator comprising:
a code-modulation circuit that code-modulates input power with a modulation code to generate code-modulated power which is alternating-current power; and
a terminal through which the code-modulated power is transmitted, the terminal being connected to a transmission path,
wherein, in code-modulation of the input power, the code-modulation circuit determines whether or not to reverse a direction of a current of the input power according to whether each bit of the modulation code is a first value or a second value.

2. The code modulator according to claim 1 ,
wherein the modulation code includes an orthogonal code.

3. The code modulator according to claim 1 ,
wherein the code-modulation circuit includes a plurality of switches.

4. The code modulator according to claim 3 ,
wherein the code-modulation circuit includes an H-bridge circuit in which four bidirectional switch circuits are connected in a full-bridge configuration, each of the four bidirectional switch circuits including a corresponding one of the plurality of switches.

5. The code modulator according to claim 3 , further comprising:
a control circuit that generates a plurality of control signals for turning on and off the plurality of switches,
wherein the code-modulation circuit code-modulates the input power, based on the plurality of control signals.

6. The code modulator according to claim 5 , further comprising:
a communication circuit that receives an instruction signal including code information regarding the modulation code and timing information regarding a timing for code-modulating the input power,
wherein the control circuit generates the plurality of control signals according to the instruction signal.

7. The code modulator according to claim 1 ,
wherein the input power is direct-current power or alternating-current power.

8. The code modulator according to claim 1 ,
wherein the modulation code includes 2n-bit data including first n-bit data and second n-bit data following the first n-bit data, n being a natural number, and
the second n-bit data are obtained by inverting bits of the first n-bit data, respectively.

9. A code demodulator comprising:
a terminal through which code-modulated power is received, the terminal being connected to a transmission path, the code-demodulated power being alternating-current power; and
a code-demodulation circuit that code-demodulates the code-modulated power with a demodulation code to generate output power,
wherein, in code-demodulation of the code-modulated power, the code-demodulation circuit determines whether or not to reverse a direction of a current of the code-modulated power according to whether each bit of the demodulation code is a first value or a second value.

10. The code demodulator according to claim 9 ,
wherein the demodulation code includes an orthogonal code.

11. The code demodulator according to claim 9 ,
wherein the code-demodulation circuit includes a plurality of switches.

12. The code demodulator according to claim 11 ,
wherein the code-demodulation circuit includes an H-bridge circuit in which four bidirectional switch circuits are connected in a full-bridge configuration, each of the four bidirectional switch circuits including a corresponding one of the plurality of switches.

13. The code demodulator according to claim 11 , further comprising:
a control circuit that generates a plurality of control signals for turning on and off the plurality of switches,
wherein the code-demodulation circuit code-demodulates the code-modulated power, based on the plurality of control signals.

14. The code demodulator according to claim 13 , further comprising:
a communication circuit that receives an instruction including code information regarding the demodulation code and timing information regarding a timing for demodulating the code-modulated power,
wherein the control circuit generates the plurality of control signals according to the instruction signal.

15. The code demodulator according to claim 9 ,
wherein the output power is direct-current power or alternating-current power.

16. The code demodulator according to claim 9 ,
wherein the demodulation code includes 2n-bit data including first n-bit data and second n-bit data following the first n-bit data, n being a natural number, and
the second n-bit data are obtained by inverting bits of the first n-bit data, respectively.

17. A controller comprising:
a processor; and
a communication circuit,
wherein the processor:
generates a first instruction signal for code-modulating first power with a first modulation code;
transmits the first instruction signal to a first code modulator via the communication circuit;
generates a second instruction signal for code-demodulating the code-modulated first power with a first demodulation code, the code-modulated first power being alternating-current power; and
transmits the second instruction signal to a first code demodulator via the communication circuit, the first code demodulator being connected to the first code modulator through a transmission path.

18. The controller according to claim 17 ,
wherein the first modulation code and the first demodulation code are the same.

19. The controller according to claim 17 ,
wherein the first instruction signal includes first code information regarding the first modulation code and first timing information regarding a timing for code-modulating the first power, and
the second instruction signal includes second code information regarding the first demodulation code and second timing information regarding a timing for code-demodulating the code-demodulated first power.

20. The controller according to claim 17 ,
wherein the first power and the second power are both direct-current power or are both alternating-current power.

21. The controller according to claim 17 ,
wherein the processor further:
generates a third instruction signal for code-modulating second power with a second modulation code;
transmits the third instruction signal to a second code modulator via the communication circuit;
generates a fourth instruction signal for code-demodulating the code-modulated second power with a second demodulation code, the code-modulated second power being alternating-current power; and
transmits the fourth instruction signal to a second code demodulator via the communication circuit,

wherein the first modulation code and the second modulation code are orthogonal to each other,
the first demodulation code and the second demodulation code are orthogonal to each other, and
the code-modulated first power and the code-modulated second power are multiplexed and transmitted through the transmission path.

22. The controller according to claim 17 ,
wherein the communication circuit is configured to communicate with a first device having a first circuit and a second device having a second circuit; and
the processor further:
obtains first power information via the communication circuit, the first power information regarding an amount of power in the first device;
obtains second power information via the communication circuit, the second power information regarding an amount of power in the second device; and
sets one of the first and second circuits as the first code modulator and sets another of the first and second circuits as the first code demodulator, based on the first power information and the se

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Nishimoto Taiki
• Yamamoto Atsushi
• Hara Shoichi
• Masuda Kohei
• Minegishi Akira

Classifications

• H02J13/1311 Primary

  using the power network as support for the transmission · CPC title

• G05B15/02

  electric · CPC title

• H02M1/08 Primary

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M2001/0048

  Electricity · mapped topic

• H04B1/69

  Spread spectrum techniques · CPC title